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41 Threads found on edaboard.com: Design Compiler Optimization
Presently I'm following the power optimization flow described in the Power compiler (Version D-2010.03-SP2) described on page 2-3. Essentially the flow is: - Simulate RTL and generate SAIF - Synthesize in DC compiler to get gate-level netlist - Place and route design - Simulate gate-level or placed netlist to generate (...)
Recently I completed an assignment where I had to remove the negative slack for a log10 calculation ASIC using deisgn compiler. I was able to remove the slack and the long paths reduced such that it could now work at 363MHz (earlier it could work at 170 MHz to meet the slack). The design compiler worked at ultra setting so the (...)
Hi, I tried to synthesize a 64-bit adder. It's pure combinational. When I set the virtual clk to 1GHz. The timing report is clock vclk (rise edge) 1.00 1.00 clock network delay (ideal) 0.00 1.00 output external delay -0.10 0.90 data required time
You are asking about analog IC design?
Hi My question is : How to force design compiler to keep the structure of my HDL design ? I have designed a combinational circuit that its structure is important to me. I want that DC put the same gates and keep the same connections between those gates and then I want to see the reports. But when I compile my (...)
I have a design which requires 32bit adders, I have made a 1bit full adder, and used generate statement in verilog to make it 32bit adder. Will grouping these 1bit adders together in design compiler help in optimization or should I just leave them as is? module fulladder(a,b,cin,sum,cout); input a,b,cin; output (...)
Hi , how to reduce high logic levels (present in datapath blocks) duirng synthesis using design compiler through better optimization ? I need proper attrbutes / any other way which can be used during synthesis so that logic level can be reduced .
Hi, Are there any techniques that I can use to make RTL compiler achieve better slack for critical path in my design ? I mean synthesis techniques not front end (pipelining and so ) Thanks
Hi I wrote verilog code for my design in gate level,but when I try to synthesize it with Synopsys design compiler, it changes my design automatically for optimization,but I don't like to change my design. I want to synthesize exactly what I wrote. Is there any way to force it to (...)
when memory requirement goes up more than available RAM size. Tool tries to use swap memory. If this is also not sufficient tool runs out memory. You can try below option. 1. Increase swap size. 2. Synthesize your design in small parts. 3. Reduce optimization effort medium/low. If is set to high. 4. Use different coding style.. Some of the the cons
Hi All, I'm familiar with Synopsys design compiler. How ICC is different? Does it just use P&R information instead of WLM? How is the flow different for the block-level synthesis? Thank you!
i just looked at the docs - generic mapping is primarily focussed on the datapath synthesis and depending on the effort you specify the optimization in your design will be executed.
Hi. Target Library: A technology library that design compiler maps to during optimization. Along with the link_library and search_path variables, you need to specify the logical library that will be used for mapping/optimization. Link Library : The technology library that contains the definition of the cells used in the (...)
Hi, In the recent research work I want to use design compiler (DC) to reduce the number of FFs in my design (the basic idea is to compare the primary outputs (POs) of one fault-free sequential design and one copy of this design - everything is the same except that one fault is injected in specific (...)
Dear Engineers. If anyone worked on power optimization using DC compiler from synopsys I have some questions and hopefully someone can help. First of all is there any tutorial for this design tool?
Hey, Synthesis is not just converting RTL or higher level design into lower level (mainly gate level). Synthesis tools like synopsys design compiler also do optimization of your design. There are various algorithms which are followed based on the design and constraints put by the (...)
Hii, I'm remapping the gate-level netlist using design compiler and I want get new gate-level netlist which include mutlibit cell. My original gate-level netlist have many 1 bit FF , and my new cell library have 2bit FF better than two 1bit FF , I want mapping them with multibit FF, how can I use DC to accomplish it. the command set hdlin
Hi, I have a design which deals with 100's of paths on which i set min/max delays and i would like to know if design compiler has any command which actually only gives me the violators out of all these paths. e.g. Suppose say i have path 1, and 2. I individually synthesize path1 and it works. Suppose path2 is added in the list of (...)
place_opt does placement + optimization, so yes, it will add buffers in the design to fix design rule violations (max_cap, max_trans), add in buffertrees for high fanout nets, and to help fix timing violations
Hi, Do we need to take care in teh synthesis, when we are going for 65nm synthesis to 40nm synthesis. Will there be any change in the tool optimization. The tool is design compiler.
Hi Srini, I am not sure , if you are still struggling with the issue. Before looking into the timing slack numbers, make sure you have the right constraints 1) proper clock definitions in correct units( DC standard unit is ns , RC standard unit of period is ps ) 2) Clock exceptions 3) design Exceptions 4) Dont USE cells 5) How are
Hi guys! I'm learning Digital design with design compiler and I want to know more about timing constraints and optimization. Synopsys has published an excellent user guide named "Synopsys Timing Constraints and optimization User Guide" but unfortunately it's in our uni's computers and we're not allowed to (...)
Hi zhipeng, incr_delay is nothing but fixing timing violation on path based. If you see incr_delay is called less time mean.. timing is almost fixed. you will see very less n prefix instances in design.. I cant understand ,why u want to call incr_delay many times..
Hello I'm runnign synthesis with design compiler. After differents synthesis my results in report timing, says that the slack is zero or negative. So my question is, because i'm looking for positive slack for a secondary power optimization, how can I see the positive slack?
I've a design full custom I wanto to synthetize and optmize my design. A part design rules, I can put optimization constraint. How can estimate input delay. I start in a top down synsthesis optimization flow after synthesis how can I estimate optimization constraint like input/ouput delay on (...)
I'm using design compiler i wanto to make a post synthesis simulation , How can I do? I wanto to rebuild ma timing constraint (optimization CONSTRAINT) after synthesis of my top module, so I can set input/ouput delay in my sub designs and than I can try re-optimize they one by one. Is it possible? Another question is related (...)
Hi All; I am trying to optimize my design using Power compiler (Synopsys) and looking for Power compiler' Usermanual and Tutorials. It seems to be not available in this forum and Synopsys site as well. Could anyone give me some advices? Many thanks in advance. W3Y
Hi designerAll, Can any one suggest me how to avoid the warning OPT-1206 in design compiler. The OPT-1206 defination is: " The register Ro is constant and will be removed ". This warns that some of the flipflop from my design are getting removed as a result of (...)
Similar operations can most easily be implemented by a FOR LOOP iterative scheme. Generally you should consider, that all equivalent design descriptions can be expected to end up in the same code due to the VHDL compiler's optimization action. Thus readability and compactness of code are the main criteria.
Hi all, Does power compiler needs seperate license or is it in-built in design compiler. Thanx Just run "report_power" command, and the DC automatically invokes P/C if licensed.
Any module may be excluded from optimization during synthesis, using the command 'set_dont_touch' command (in Synopsys design compiler) Usage: set_dont_touch
Hi, Please can somebody help on what kind of basic design compiler questions to expect on an interview. Appreciate your help! Sincerely, Shubha
I have a few question : (1) I need a complete library pack including technology library ( for optimization ) , link library, symbolic library and especially a verilog or VHDL code to describe the library's elements. The technical library must contain both timming model as well as SDPD for power modelling ( Leakage and Internal ) .... If anyone c
I want this specific document on retiming in synopys DC compiler "design compiler reference manual: register retiming" Please post the manual if you have.
Can anyone tell me the techniques of how to optimize the design by taking 1.Restructuring netlist 2.Remapping logic 3.Swapping pins
Hi all, I am new to design compiler. What's the main difference with dc_shell, dc_shell-t, dc_shell-xg-t? Thanks! Davy
actually, power compiler extract clock gating on your design for power saving. while only prime power does the power analysis. the general flow is as follows: 1. read_verilog 2. read_spef (if available) 3. read_vcd 4. calculate_power 5. report_power you can get the detail usage in Prime Power. have fun...
actually i'm comfortable with DC. now i have to use RTL compiler. what r the issues i need to take care? anybody expalin the differences between synopsys DC & cadence RTL compiler interms of the synthesis process, design handling, constrainnig, timing etc..
PT timing engine is much more accurate than the design compiler. PT is used as sign off tool, while the timing engine in DC is just to provide DC some timing sense in optimization
design compiler refrence manual: register retiming design compiler refrence manual: optimization and Timing design compiler refrence manual: Constraints and Timing design compiler : Command-Line Interface Guide
Change naming rule, eliminate *cell*, it's not fit for back-end design, also make sure no \ exist.