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41 Threads found on edaboard.com: Design Compiler Optimization
Hi, Once you change the netlist for whatever reason, it should be a bunch of things to do afterward. - Formal verification - DFT insertion - CTS, Place & Route. In case of your flow, there MUST have some guidance for p&n steps from the last step. So that, the final design would have better power consumption.
Recently I completed an assignment where I had to remove the negative slack for a log10 calculation ASIC using deisgn compiler. I was able to remove the slack and the long paths reduced such that it could now work at 363MHz (earlier it could work at 170 MHz to meet the slack). The design compiler worked at ultra setting so the (...)
Hi, I tried to synthesize a 64-bit adder. It's pure combinational. When I set the virtual clk to 1GHz. The timing report is clock vclk (rise edge) 1.00 1.00 clock network delay (ideal) 0.00 1.00 output external delay -0.10 0.90 data required time
You are asking about analog IC design?
Hi My question is : How to force design compiler to keep the structure of my HDL design ? I have designed a combinational circuit that its structure is important to me. I want that DC put the same gates and keep the same connections between those gates and then I want to see the reports. But when I compile my (...)
I have a design which requires 32bit adders, I have made a 1bit full adder, and used generate statement in verilog to make it 32bit adder. Will grouping these 1bit adders together in design compiler help in optimization or should I just leave them as is? module fulladder(a,b,cin,sum,cout); input a,b,cin; output (...)
Hi , how to reduce high logic levels (present in datapath blocks) duirng synthesis using design compiler through better optimization ? I need proper attrbutes / any other way which can be used during synthesis so that logic level can be reduced .
Hi, Are there any techniques that I can use to make RTL compiler achieve better slack for critical path in my design ? I mean synthesis techniques not front end (pipelining and so ) Thanks
Hi I wrote verilog code for my design in gate level,but when I try to synthesize it with Synopsys design compiler, it changes my design automatically for optimization,but I don't like to change my design. I want to synthesize exactly what I wrote. Is there any way to force it to (...)
Hi all, I'm using Synopsys design compiler to synthesize my design written in verilog HDL. while synthesizing DC tool is throwing a message as " The tool has just run out of memory: Memory allocated = 3863 MB, Request size = 49152 displys some numbers here .... Out of memory. (Memory allocated = 3955760 K bytes)
Hi All, I'm familiar with Synopsys design compiler. How ICC is different? Does it just use P&R information instead of WLM? How is the flow different for the block-level synthesis? Thank you!
i just looked at the docs - generic mapping is primarily focussed on the datapath synthesis and depending on the effort you specify the optimization in your design will be executed.
Hi. Target Library: A technology library that design compiler maps to during optimization. Along with the link_library and search_path variables, you need to specify the logical library that will be used for mapping/optimization. Link Library : The technology library that contains the definition of the cells used in the (...)
Hi, In the recent research work I want to use design compiler (DC) to reduce the number of FFs in my design (the basic idea is to compare the primary outputs (POs) of one fault-free sequential design and one copy of this design - everything is the same except that one fault is injected in specific (...)
Dear Engineers. If anyone worked on power optimization using DC compiler from synopsys I have some questions and hopefully someone can help. First of all is there any tutorial for this design tool?
Hey, Synthesis is not just converting RTL or higher level design into lower level (mainly gate level). Synthesis tools like synopsys design compiler also do optimization of your design. There are various algorithms which are followed based on the design and constraints put by the (...)
Hii, I'm remapping the gate-level netlist using design compiler and I want get new gate-level netlist which include mutlibit cell. My original gate-level netlist have many 1 bit FF , and my new cell library have 2bit FF better than two 1bit FF , I want mapping them with multibit FF, how can I use DC to accomplish it. the command set hdlin
Hi, I have a design which deals with 100's of paths on which i set min/max delays and i would like to know if design compiler has any command which actually only gives me the violators out of all these paths. e.g. Suppose say i have path 1, and 2. I individually synthesize path1 and it works. Suppose path2 is added in the list of (...)
place_opt does placement + optimization, so yes, it will add buffers in the design to fix design rule violations (max_cap, max_trans), add in buffertrees for high fanout nets, and to help fix timing violations
Hi, Do we need to take care in teh synthesis, when we are going for 65nm synthesis to 40nm synthesis. Will there be any change in the tool optimization. The tool is design compiler.