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25 Threads found on edaboard.com: Design Compiler Ram
Hi, I have a design which has a 100Kbit Sram. I have been able to synthesize my circuit with design compiler and I know the gate count (total area divided by smallest NAND2 area) of all circuit except the ram. I don't have any memory compiler to find its actual size. I just need a rough (...)
Hi all, I'm using Synopsys design compiler to synthesize my design written in verilog HDL. while synthesizing DC tool is throwing a message as " The tool has just run out of memory: Memory allocated = 3863 MB, Request size = 49152 displys some numbers here .... Out of memory. (Memory allocated = 3955760 K bytes)
I have a small design which includes a macro ram block and am trying to perform the Place and Route in IC compiler. Is there any particular guidelines that I need to follow. I create a floorplan and then fix the ram macro which seems to be required before doing the placement. When I perform routing using route_zrt, I am (...)
I have a small design which includes a macro ram block and am trying to perform the Place and Route in IC compiler. Is there any particular guidelines that I need to follow. I create a floorplan and then fix the ram macro which seems to be required before doing the placement. When I perform routing using route_zrt, I am (...)
Hi, I have technology library for 2048x32 ram and I want to use it with my VHDL design in Cadence RTL compiler. This library contains *.lib flies and VHDL simulation model. When I include this ram as a component in my VHDL code the RTL compiler interpret it as a black box. Do I need a VHDL file for this (...)
Hi I have a main question. I have a design which I want to insert ram module in the top module. I generated rams with Artisan but I don't know how can I insert them in top?
I'm working on asic design with tsmc 130nm. Within the design I need a user-defined ram. What is the commonly used way to generate some? Are there tools for free? Until now I got the tsmc StdCell and I/O library.
I don't particularly know the Xilinx DDS compiler, but similar tools from other vendors are generating the full DDS design, including LUT or alternative sine generation schemes. You just enter the specification: frequency and amplitude resolution, clock rate and features (e.q. quadrature output, AM, FM etc.). You don't need Matlab or manual LUT gen
How to get these memory compilers? one easy solution is to check ARM website. Artisans(currently ARM) memory compilers can be download by their free library program. Since u need a memory to talk with ur processor, check Artisan library, i think they have register file compiler which could be more suited to ur need than the (...)
hai all, plz check and correct steps to create memory block 1) i started RTL coding size of ram design is datawidth=8,addresswidth=8 2) next steps i start with design compiler from that i generated ram netlist,sdc,sdf 3)using ram netlist,sdf,sdc as input to PRIMETIME from that (...)
hai all, plz check and correct steps to create memory block 1) i started RTL coding size of ram design is datawidth=8,addresswidth=8 2) next steps i start with design compiler from that i generated ram netlist,sdc,sdf 3)using ram netlist,sdf,sdc as input to PRIMETIME from that (...)
Target Library is the library, which you will use to 'map' your RTL onto. There can be multiple target libraries. where as link library is the library, which you may use to 'link' sub modules of your design such as ram/rom etc. dc will use the operating conditions, from the target library. you can set the oprating conditions by using set_operatin
Hi, Test compiler requires that you have a functional model in your library for each leaf cell in your design. Test compiler uses the functional model to perform test pattern generation. If you use cells that don't have a functional models, TC displays the warning you mentioned. So just check the ram models. Rgds, CSuresh
Hi every one... I'm new to this domain... i'm working on a design that uses large ram's... that is the depth of the ram is only 64byte... but i've to use many such ram's in parellel... could any one give me idea of the a verilog model of the ram... and how to instantiate it in the synthesiser... (...)
Hey, i need ram library files for my design.. Is there any site , where i can get it..? Is there library file for 64 bytes ram..?..
Mostly memomry is design by hand. There are some company supply an IP called Memory compiler.
Hi I'm making some tests concerning memory and I would need a single port ram and a ROM memory of 16k x 8 (128kbits) in a 0.8?m technology. I need the cells with the decoders included. Actually I need a full cell but the I/O cells. I would need all files (HDL, sim and GDS, as well as technology files to load the design into Cadence or Ledit)
I use ARTISAN to generate ram, and get the LEF file. But it doesn't work well. The tool is silicon ensemble. I import the LEF file of cell library first, and then import the LEF file of memory, It always said "Invalid token here OR missing space between token and ":"" It drives me crazy.
To "instantiate ram" means to explicitly put a ramB* library module into your HDL. Refer to your "Libraries Guide" chapter "design Elements" section "ramB16_*". To "infer ram" means to create an HDL register array that the compiler automatically recognizes as a ramB* (...)
Is the gate number of ram/ROM included in the report of synthesis? Or,only the area of the whole design including the ram/ROM is reported?