411 Threads found on edaboard.com: Design Counter
Therefore, I don't need basically to write it in the Verilog. It is juts an abstract idea for understanding the counter and the sum itself? In other words, the pseucode represent the whole looping of the design.
I'm assuming that you got the pseudo code as part of your assignment and you are supposed to write Ve
PLD, SPLD, GAL, CPLD, FPGA Design :: 11-29-2016 00:55 :: ads-ee :: Replies: 4 :: Views: 455
No, there's no counter involved in SRAM design, just row and column address decoder. Where did you get the idea?
ASIC Design Methodologies and Tools (Digital) :: 11-19-2016 15:16 :: FvM :: Replies: 4 :: Views: 742
I am trying to debug my ALU design in FPGA. I am using trigger immediate option after downloading the bit stream to FPGA. But the chipscope never displays the signal values starting from program counter=0 and the waveform starts from some other value of program counter. How to resolve this issue, I need to capture rea
PLD, SPLD, GAL, CPLD, FPGA Design :: 10-14-2016 15:16 :: ads-ee :: Replies: 5 :: Views: 703
Not exactly sure of the educational benefit of this kind of design except to point out how bad it glitches when you do asynchronous stuff like this.
The problem with the current version of your design is the RST pin of the middle FF is connected to the other two FFs and the output of the NAND. The only connection to the RST pin of the middle FF sh
Elementary Electronic Questions :: 09-02-2016 14:46 :: ads-ee :: Replies: 7 :: Views: 2353
I have a design created in Hspice. I want to verify this hspice netlist against some input stimuli. Is there a tool that I can use for this?
For example, Suppose I designed a 4 bit counter using T FFs. Is it possible to verify if the counter is functionally working correct using some tool given the (...)
ASIC Design Methodologies and Tools (Digital) :: 07-14-2016 00:06 :: maestroharsh :: Replies: 4 :: Views: 638
There are 2 ways to design synchronous FIFO that I know:
1. Using n+1 bit counters for write pointer and read pointer. In this case, since it is 8 location FIFO, you can use 3+1 = 4 bit counter. To detect full and empty is simple:
FULL: WP-RP = 4'b1000
We cannot decide full and empty conditions based on MSB. This (...)
ASIC Design Methodologies and Tools (Digital) :: 06-21-2016 18:55 :: abhiverma812 :: Replies: 2 :: Views: 1963
FPGA synthesis tools have timing analysis to check if a design is able to run at the intended clock frequency and usually also implement timing driven synthesis to tune the design for maximum speed if required. So the first step would be to write suitable timing constraints and determine the achievable counter speed.
Not knowing the used (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 05-31-2016 22:03 :: FvM :: Replies: 13 :: Views: 793
There are special design methodologies for sequential asynchronous circuits. Following these methods, it can be possible.
You only mentioned a bare idea instead of giving a logic circuit. Thus we can't see how your design fails.
ASIC Design Methodologies and Tools (Digital) :: 05-30-2016 10:25 :: FvM :: Replies: 2 :: Views: 461
I am trying to synthesize a counter which has 16 instances only.while doing cts it is giving high utilization more than 100% so it is aborting.
I have started the design with 20% util because it gave problem with 40% util.please some one say me the fix.
ASIC Design Methodologies and Tools (Digital) :: 05-28-2016 16:01 :: cyrax747 :: Replies: 3 :: Views: 631
Hello Dave, please find my code below:
always@(posedge clk,negedge reset)
dout <= 0;
dout <= din;
ASIC Design Methodologies and Tools (Digital) :: 04-18-2016 04:10 :: spandus :: Replies: 2 :: Views: 619
I am a just-graduated engineer and right now I am doing an internship in Japan. My task is to develop a SMPTE time code decoder on a FPGA ALTERA DE0 TERASIC and display the time-code on the 7-segment displays.
I have attended two courses at the university about digital design, but up to now I have no practical experience and unfortunat
PLD, SPLD, GAL, CPLD, FPGA Design :: 04-05-2016 01:39 :: orso135 :: Replies: 9 :: Views: 1597
Your question doesn't make sense and also it is in the wrong community! No wonder till now there were no replies.
How can you write a TB for just ANY example netlist? If you don't know the functionality of the netlist you cannot write a TB.
Create a simple design (say a 3 bit counter) and generate its netlist. Then write the TB for it (in fact eve
Software Links :: 03-02-2016 10:22 :: dpaul :: Replies: 3 :: Views: 44
You should be able to get the details from a processor design manual/spec. At a very high level, instruction cache is the cache memory which stores the instructions that will be executed sequentially in a processor. The program counter will point to the memory address of the instruction that needs to be fetched, the I-cache controller looks up the
ASIC Design Methodologies and Tools (Digital) :: 01-25-2016 22:37 :: saurabhr8here :: Replies: 1 :: Views: 625
Your tff component doesn't work, because input t isn't used in the logic. And it won't compile in your design because it has an unconnected reset input without default value.
PLD, SPLD, GAL, CPLD, FPGA Design :: 12-20-2015 23:18 :: FvM :: Replies: 11 :: Views: 1065
The code in post #1 isn't related to UART, just sending 8-bit words. It's neither implementing a 32-bit counter.
Apparently you copied a third parties code that is loosely related to the thread topic, but doesn't actually help to solve it.
Writing a programmable logic design starts with a specification:
- input and output signals
PLD, SPLD, GAL, CPLD, FPGA Design :: 12-18-2015 07:46 :: FvM :: Replies: 4 :: Views: 650
This is probably a timing issue from poor design practice. Generating a clock with logic can be prone to timing issues. I would move the counter in to the clock domain and your problems may go away
PLD, SPLD, GAL, CPLD, FPGA Design :: 12-12-2015 16:54 :: TrickyDicky :: Replies: 4 :: Views: 705
Although variable usage for tx_reg and counter reduces the achievable design speed (creates large combinational pathes), the design looks functional.
How did you stimulate tx_data_bus in your hardware test?
PLD, SPLD, GAL, CPLD, FPGA Design :: 12-10-2015 13:00 :: FvM :: Replies: 5 :: Views: 779
I am using vivado 2015.2.1 . I designed up-down counter. I am getting error. (mentioned below)
Find my code below:
input wire reset,clk, uphdnl,count;
//output reg out0,out1;
output reg sseg;
output reg an;
PLD, SPLD, GAL, CPLD, FPGA Design :: 10-11-2015 20:45 :: Kuldeepluvani :: Replies: 3 :: Views: 2507
Tricky question because if you use some conceptual design as shown it is not real design, then all you can use are block diagrams.
Then you must dream up your own logic symbols using standard shapes and text.
Not very good for detail oriented Engineers but perhaps ok for your purposes.
For example the Johnson counter you have (...)
Software Recommendations :: 08-09-2015 21:23 :: SunnySkyguy :: Replies: 10 :: Views: 127
This is my first post on this forum, so bear with me!
First some background:
I'm currently studying Electrical and Electronic Engineering and I've been tasked by my company to design a prototype PCIe card for testing PCIe connection functionality on our products. This is part of my final project for the course, which has to be work-based
PLD, SPLD, GAL, CPLD, FPGA Design :: 08-06-2015 10:33 :: Andy Seager :: Replies: 2 :: Views: 505