Search Engine

391 Threads found on Design Sigma Delta
I have a digital ic deaign experience around 12 years include graduated school. I worked 8 years world No. 1 semiconductor company. possible 1. RTL design , Synthesis, STA and p&r by synopsys tool 2. design a testchip for ip verification.( IO, i2c, spi interface) 3. Digital logic in Analog block (AFC, sigma (...)
Hello all, I want to design a model of a MASH 1-1-1 ( 3rd order sigma delta modulator) in Verilog A. I am new to VerilogA and i am having trouble designing it, especially the delays of the error cancellation network. Any help will be greatly appreciated. Thank you in advance
I am trying to design a 3rd order SD modulator ( MASH 1-1-1 topology ), but with reduced hardware. That means, that only the first accumulator will have full length ( N ) and the other two accumulators will have reduced lengths ( L < M < N ). According to the literature, in order to get the maximum sequence length, we set the LSB of the input to
Hi Altruists, I need to design an incremental sigma delta ADC (OSR=500) where I need to implement a CoI Filter. From literature study i found that this CoI filter is actually same as CIC but without the comb part for CIC. I need to write a code in Verilog (or Verilog A) for CoI Filter. I dont have so much deep knowledge on CIC. I checked (...)
Hi Folks, I need to design a 1 bit DAC for sigma delta modulator. Can anybody please suggest me some architecture for dac design? For incremental delta sigma the dac needs to provide three state ( two states from two quantizer levels and one state for input level). How is it possible (...)
Hi, I need help to determine the op amp gain required to match certain ADC specifications. I need to design a delta sigma 14 bit ADC and need to find out required op-amp gain for the integrator design. Is there any certain formula to find out that
Hello, I?ve got problem with my 3 Stage Filter design in MATLAB (for a delta-sigma Modulator), it would be great if someone could help! The delta-sigma modulator has an input signal of 1kHz and wir OSR = 512 an output of 1 MHz. So I decided to do a 3 stage Filter: CIC w. 1 Bit input (decimation (...)
Hi, i want to realize a fully digital closed loop pwm modulator for my class d amplifier but i've no idea on how to start with my design. Googling i've found sigma delta modulator and self-oscillating class d amplifier implemented in analog way (input+feedback -> integrator -> comparator -> flip-flop). At the moment the mosfets of my (...)
I am working on sigma delta modulators. I came to know that the MIXMODEST presentation/document provides an excellent description of the factors related to the design of sigma delta modulators. the link given below does not work. Can anyone forward me the docu
hi, i'm trying to design a sigma delta modulator using matlab i'm expecting a digital stream where impulse frequency changes for ex when applying a sine wave as input but what i found is a bit stream with constant frequency i had attached the matlab code, the sample time is Fs * 64, kind regards, abdoo
Hello everybody! Recently I have designed a 2nd order Incremental sigma-delta ADC. I have two main concerns about my design: 1 - The goal was achieving at least 14 bits, but unfortunately after realizing the FFT in order to obtain the outuput spectrum, the fundamental is attenuated by 20 dB. I don't know which reasons can (...)
hello all !!!!!! I need a simulink model of a quadrature sigma delta modulator and the matlab code to calculate the psd of the output. Can anyone help me with that???
hi my friends I want to design an delta sigma ADC, and i need to amount of minimum jitter in my Calculation. what is the amount of jitter in TSMC 0.13 ?
Dear all, What is the best book to go deep into asynchronous sigma delta modulators, from system level down to circuit design? Thank you a lot for your help :)
Hi all, i am trying to design a sigma delta modulator in pspice by ABM library , here it is my schematic , nut it dont work! first block subtract the input from output , then the result goes to integrator and then if the result is positive the output becomes 5 , else the output becomes zero and this output goes to 74175 that its clock rate (...)
Hello everyone For switches What kind of pin input and output should be? Thank you 114261 114262
Limit cycles and and some spurios compnents are generated by design and can be reproduced in a simulation with ideal circuit elements, other interferences are caused by non-ideal hardware properties. You should be able to sort out which kind of interferences shows in your case.
I want to design a NTF for DSM with complex zeros such that the in-band noise is minimized. Is there any any algorithm (can be implemented in MATLAB) that I can use to place the zeros ??? Thanks!
hi i am designing a sigma delta adc. \can i keep a osr which is not in powers of 2 eg. 50. will i be able to design a decimation/\cic filter for such a decimation factor?? or is it necesaary to keep \osr in powers of 2???