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## Design Sigma Delta |

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391 Threads found on edaboard.com: **Design Sigma Delta**

I have a digital ic deaign experience around 12 years include graduated school.
I worked 8 years world No. 1 semiconductor company.
possible
1. RTL **design** , Synthesis, STA and p&r by synopsys tool
2. **design** a testchip for ip verification.( IO, i2c, spi interface)
3. Digital logic in Analog block (AFC, **sigma** (...)

EDA Jobs :: 03-17-2017 11:55 :: taepyeong :: Replies: **0** :: Views: **3573**

Hello all,
I want to **design** a model of a MASH 1-1-1 ( 3rd order **sigma** **delta** modulator) in Verilog A.
I am new to VerilogA and i am having trouble **design**ing it, especially the delays of the error cancellation network.
Any help will be greatly appreciated.
Thank you in advance

Analog Circuit Design :: 03-02-2017 09:49 :: NikosTS :: Replies: **1** :: Views: **1222**

I am trying to **design** a 3rd order SD modulator ( MASH 1-1-1 topology ), but with reduced hardware. That means, that only the first accumulator will have full length ( N ) and the other two accumulators will have reduced lengths ( L < M < N ).
According to the literature, in order to get the maximum sequence length, we set the LSB of the input to

Digital Signal Processing :: 02-28-2017 13:59 :: NikosTS :: Replies: **0** :: Views: **659**

Hi Altruists,
I need to **design** an incremental **sigma** **delta** ADC (OSR=500) where I need to implement a CoI Filter. From literature study i found that this CoI filter is actually same as CIC but without the comb part for CIC. I need to write a code in Verilog (or Verilog A) for CoI Filter. I dont have so much deep knowledge on CIC. I checked (...)

Analog Circuit Design :: 02-13-2017 21:08 :: ashrafsazid :: Replies: **0** :: Views: **818**

Hi Folks,
I need to **design** a 1 bit DAC for **sigma** **delta** modulator. Can anybody please suggest me some architecture for dac **design**?
For incremental **delta** **sigma** the dac needs to provide three state ( two states from two quantizer levels and one state for input level). How is it possible (...)

Analog Circuit Design :: 02-05-2017 03:47 :: ashrafsazid :: Replies: **1** :: Views: **797**

Hi,
I need help to determine the op amp gain required to match certain ADC specifications. I need to **design** a **delta** **sigma** 14 bit ADC and need to find out required op-amp gain for the integrator **design**. Is there any certain formula to find out that

Analog Circuit Design :: 10-01-2016 09:30 :: ashrafsazid :: Replies: **0** :: Views: **574**

Hello,
I?ve got problem with my 3 Stage Filter **design** in MATLAB (for a **delta**-**sigma** Modulator),
it would be great if someone could help!
The **delta**-**sigma** modulator has an input signal of 1kHz and wir OSR = 512 an output of 1 MHz.
So I decided to do a 3 stage Filter: CIC w. 1 Bit input (decimation (...)

ASIC Design Methodologies and Tools (Digital) :: 09-21-2016 13:29 :: hyperbolicus :: Replies: **0** :: Views: **913**

Hi, i want to realize a fully digital closed loop pwm modulator for my class d amplifier but i've no idea on how to start with my **design**.
Googling i've found **sigma** **delta** modulator and self-oscillating class d amplifier implemented in analog way (input+feedback -> integrator -> comparator -> flip-flop).
At the moment the mosfets of my (...)

Analog Circuit Design :: 07-17-2016 18:38 :: franticEB :: Replies: **1** :: Views: **426**

I am working on **sigma** **delta** modulators.
I came to know that the MIXMODEST presentation/document provides an excellent description of the factors related to the **design** of **sigma** **delta** modulators.
the link given below does not work.
Can anyone forward me the docu

Analog Circuit Design :: 03-08-2016 06:20 :: pankaj jha :: Replies: **0** :: Views: **452**

hi,
i'm trying to **design** a **sigma** **delta** modulator using matlab
i'm expecting a digital stream where impulse frequency changes for ex when applying a sine wave as input
but what i found is a bit stream with constant frequency
i had attached the matlab code,
the sample time is Fs * 64,
kind regards,
abdoo

Digital Signal Processing :: 01-28-2016 16:15 :: abdoo :: Replies: **2** :: Views: **739**

ASIC Design Methodologies and Tools (Digital) :: 11-06-2015 12:08 :: SunnySkyguy :: Replies: **2** :: Views: **872**

Hello everybody! Recently I have **design**ed a 2nd order Incremental **sigma**-**delta** ADC. I have two main concerns about my **design**:
1 - The goal was achieving at least 14 bits, but unfortunately after realizing the FFT in order to obtain the outuput spectrum, the fundamental is attenuated by 20 dB. I don't know which reasons can (...)

Analog Circuit Design :: 10-15-2015 14:04 :: mark4444 :: Replies: **5** :: Views: **886**

hello all !!!!!!
I need a simulink model of a quadrature **sigma** **delta** modulator and the matlab code to calculate the psd of the output.
Can anyone help me with that???

Analog Circuit Design :: 10-07-2015 13:05 :: pankaj jha :: Replies: **0** :: Views: **558**

hi my friends
I want to **design** an **delta** **sigma** ADC, and i need to amount of minimum jitter in my Calculation.
what is the amount of jitter in TSMC 0.13 ?

Analog Circuit Design :: 07-29-2015 12:19 :: rey1991 :: Replies: **1** :: Views: **493**

Dear all,
What is the best book to go deep into asynchronous **sigma** **delta** modulators, from system level down to circuit **design**?
Thank you a lot for your help :)

Analog Circuit Design :: 04-24-2015 15:49 :: metalgarri :: Replies: **0** :: Views: **485**

Hi all,
i am trying to **design** a **sigma** **delta** modulator in pspice by ABM library , here it is my schematic , nut it dont work!
first block subtract the input from output , then the result goes to integrator and then if the result is positive the output becomes 5 , else the output becomes zero and this output goes to 74175 that its clock rate (...)

Analog Circuit Design :: 04-02-2015 05:41 :: zizi110 :: Replies: **2** :: Views: **741**

Hello everyone
For switches
What kind of pin input and output should be?
Thank you
114261
114262

Analog Circuit Design :: 02-14-2015 08:15 :: Joe_Bel :: Replies: **1** :: Views: **602**

Limit cycles and and some spurios compnents are generated by **design** and can be reproduced in a simulation with ideal circuit elements, other interferences are caused by non-ideal hardware properties. You should be able to sort out which kind of interferences shows in your case.

Analog Circuit Design :: 01-31-2015 12:31 :: FvM :: Replies: **3** :: Views: **571**

I want to **design** a NTF for DSM with complex zeros such that the in-band noise is minimized.
Is there any any algorithm (can be implemented in MATLAB) that I can use to place the zeros ???
Thanks!

Analog Circuit Design :: 01-22-2015 16:06 :: electronhole :: Replies: **1** :: Views: **515**

hi
i am **design**ing a **sigma** **delta** adc. \can i keep a osr which is not in powers of 2 eg. 50. will i be able to **design** a decimation/\cic filter for such a decimation factor?? or is it necesaary to keep \osr in powers of 2???

Analog Circuit Design :: 12-01-2014 12:25 :: pankaj jha :: Replies: **0** :: Views: **486**

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gain common source | layout clock gate | cadence model library setup | timing simulation xilinx | snr and ber for matlab | cadence simulation example | vpd file | drc cadence | hfss tutorial waveguide | mux library