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clock sync , sync flops , sync generator , pll sync
76 Threads found on edaboard.com: Design Sync
In my noob viewpoint, the advantage of using this component is the possibility of the tool to provide to the designer the ability to have a visual way to assign clocks to other modules through the same avalon interface, avoiding sync errors. Just a guess...
Hi, It could be IC design, VHDL, or C... --> It depends on the context. Klaus
Dear all, I am trying to design an avr for regulating the output of 230volt ac generator. avr input voltage-230 volt ac avr out put voltage -8 to 15 v feed back to generator excitation coil Please help me solve the error amplifier problem of sg3525 .I?m using sg 3525 with ir2010 sync buck converter design. Irf840 (...)
Chop mode is design to lock to not sync to the incoming repetitive signal but lock to an offset with at least 100 Hz difference frequency to create a smooth trace. Alt mode synchronizes to the selected polarity from the selected source and with retrace blanking , may or may not be synchronous to the incoming signal. (...)
Doesnt really make sense as I have no idea what component you are using. The easiest thing for you would be to make a testbench, so that with a known set of inputs and outputs, you can check your design is working correctly.
You are willing to perform what is called a synchronous design and it is recommended you take a research on the subject 'state machines'. As it is your first design and the purpose is certainly learning, you will do manually the steps of the design instead using a tool for that. Basically, at the end of each functional (...)
Hi All, I have a design related question on CDC. I have two black boxes working async. to each other and i am not aware of both the clk speed. Is it feasible to insert a sync. for the data / ctrl signal that is needed to pass data properly between the two black boxes. I need to design such sync. (...)
Hi. I'm not sure as to AHB Protocol Checker. It probably was in coretex M design kit. is this something like verification? Does anyone know as to AHB Protocol Checker?
Hi, I tried to search the forum, but didn't get an answer. I have a process of 250MHz, of which 62.5MHz is created. I want to cancel it and use a PLL. Since this is a working design, I need to 'blend in' without making a mess... My problem is that in the current process of the making of the 62.5MHz clock, other control signals are used for othe
The AND gate sees two inputs changing at the same time. Depending on timing, a false pulse condition can occur. This is known as a race condition and to avoid the condition must be disabled during data transitions or sync'd with the same clock. "Ripple" counters are notorious for glitches unless you design a method to avoid the race condition.
I guess, the clock CLK is not used by any flop in the design...
I have a montonicity issue with my DAC with worst case DNL during transition from 0111 1111 to 1000 000. There is a massive glitch during this transition. the output impedance of current source I designed is very high 10Mohms. I have noticed the glitches in certain bits from the D flip flop outputs which inputs the signal to the switches of the cur
is a design of a clock based on popular lamp VFD IW-18. The name PipeBOMB is due to the fact that the clock looks like a bomb. It also is equipped with a function of counting down to a pseudo explosion (CountDown counter). The lamp is controlled by drivers Maxim MAX6920. Atmega32
I want to design a synchronous counter with 12 states and synchronous reset by connecting the overflow signal ( CT =15 ) directly to load input ( /M2M1 ) so that I can start the counter at a custom state, what I'm thinking of doing right now is just put flip-flops pre-loaded with my predefined start state at the input of the counter so that (...)
No problem with them friend just count on till it counts 4 which is 100 then instead of 101 (5) the outputs of 1st and 3rd ff are NAND and fed to the CLR pins of the 3 FF this resets them and starts the count from 000 to satiate your need PS I made a small error in my first post and have rectified it here do check it up - - - U
How to balance the skew if we have two clocks domains in a design. Please help
Dear Sherlock, Tektronics have long been for >50yrs masters of the trigger design. They use a wide variety of input signal conditioning for HPF, LPF and once used a PLL for retriggerable stable windowed time base control. They also have video trigger so the negative sync pulses are not used but rather the flat level after sync pulse which is (...)
75304 Hi all, In my design there is a TI transcever tlk2211 interfaces to spartn6, which send data(RD) in ddr mode, and sourced with two inverted clk(RBC0/1) to capture the data in each of the rising edge. the waveform as shown in the attachment, I'm a little puzzled how should I capture the data and sync t
Hi All, Why we are using Asynchronous Reset in our design...? What are the advantages of Asynchronous Reset...? What happens if we use synchronous Reset...? Thanks in Advance..
you should have synchronized the component links first before you imported the design changes into the pcb. The command is under >>Project >> Component links. Altium keeps a unique id for every component. As long as they are still the same it should not be a problem to sync the schematics and pcb.