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45 Threads found on edaboard.com: Design Ware
Dear all When I try to synthesis the design ware example in DC and give the clk some period why am I not able to see the clk period in the timing report or the report_qor! it says critical path slack as uninit and critical psth clk period as n/a ! Please let me know. Thank you
Dear All, How to confirm if the re timing has worked in example (DW_mult_pipe Stallable Pipelined Multiplier) given in design ware library? There are two description as in before pipeline re timing and one after pipeline re timing, but while using balance register in synposys DC it does not allow re timing saying " No movable flip-flops in d
Hi. As I know, design ware library has multiplier cell library.but I don't know What is the benefit the using designware multiplier Library versus custom multiplier(like booth algorithm)? Does anyone know what is different and pros &cons each them?
I'm am trying to simulate some VHDL codes that use Synopsys design ware components in modelsim. I added the design ware vhdl files to a directory called Dware in my work directory. I have successfully compiled some files(they include Dware). but there is onlyone file that produces the (...)
Is dw_foundation.sldb listed in both the synthetic_library and the link_library variables *prior* to your read/analyze/elaborate/link/compile steps? Run and examine the link command output; check_design might also be useful. Also make sure you are not seeing any related messages during the earlier analyze/elaborate steps. (e.g. double-check you are
You need to use a LC low-pass filter. Check this at page 12.
Software request here is done for all the related companies to design a soft ware for the medical electronic record to keep in the software so necessary thing is to manage it properly for controlling the medical department in all respect.
plz help me to design a simple hard ware trojan circut using verilog code..its for my accademic seminar..
Well synopsys has its own memory compilers ( ). If you get those, it will be added to the design ware libraries used by DC.
hello everybody anyone can help me to find an academic study XXXXXXXXXXXX which study well,the inverters designs (topology) using in the LCD monitor (CCFL load of course): 1) Buck Royer inverter. 2) Push pull inverter. 3) Half Bridge inverter. 4) Full Bridge inverter. and the light tuning methods using inverter IC. thanks for all.
can any one tell me the companies that take fresh graduate to work as Digital ASIC Senior design Engineer in Egypt I will graduate after 1 month I want to ask also if i should send now or when i finish my graduation project discussion
Job Name : Junior Analog design Engineer( JDAE) Department : ASIC Location : Cairo Responsibilities : design of analog blocks and IP components mentored by our senior designers, from design phase to test and characterization. Responsible for all aspects of development including design, simulation and (...)
hello all , i want work whit magnetic designer soft ware to design the transformer for use in pspice , but in manual of this soft ware graphic that you can use the transformer that you design in isspices environment ., now i dont know that whether i can use isspice library to pspice library and use it or (...)
dear all i need for clear some concepts in synthesize operation i need to know during design stage: what is best way for design is it via ahardware side or software side ? is i deal with vhdl as hifh level language or must take in my consideration every thing write in vhdl must represent by hard (...)
Hi I'm using Coventor ware tool for designing the capacitor. I have struck in meshing for an particular design. the mesh (same mesh type for all layers in design) that i have tried is taking about 7 hours for mem mech simulation. Please help me to get rid of this problem (about meshing). can i do different mesh for (...)
hi, I'm using coventor ware for mems based inductor design. can anyone tell me how to draw the (planar) circular coil and also provide the related equations.
you can use any one orcad capture or allegro design cis not a problem
hi all! i have a small problem about my simulation of array antenna based on my master of science thesis based on the topic "modelisation and design of patch array antenna for emision and reception of internet (WIMAX) signal". the problem concern the validation check step on HFSS11 soft ware. can some on help me?
hi, i need to design a multiband (2.4/5.2/5.8 GHz)antenna for ism band using CST microwave studio soft ware. how can i do that ? thnx
Welcome to EDA Board The instruments you wish to design are not simple. we need to know how much experience do you have in electronics and microcontrollers to help you. Best of luck Nandhu