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Hello, I have the same problem. I was aware enough for the different link commands between DC (link_library) and PT (link_path) but I still have the same problem when I read_ddc file.ddc Unable to resolve reference to x1 in top-level Creating black box for x1 Any hints? Thanks
Hi guys, If I select a net in a verilog module, is it possible to find the primary inputs that my net depend in designcompiler? I already tried the report_transitive_fanin but i have registers in my circuit and this command have a problem because the fanin report stops at the clock pins of registers. Thanks, DustHerder
Hello, During a post synthesis power analysis I'm loading a parasitics file generated in designcompiler. I get following warning in PrimeTime : Warning: Reduced annotation reading must be enabled before reading a parasitics file which contains reduced annotations. (PARA-123) Can anyone please tell me how to enabl
Check inside dc_shell your synthetic_library wariable. It should contains something like dw_foundation.sldb with path to this sldb library. Usually, this libray comes with designcompiler. Something like ./libraries/syn/dw_foundation.sldb The DW_ram_rw_s_dff.v is for simulation only, not for synthesis. For synthesis, DC will use description from sl
Hi, My SDF file generated by Encounter does not specify setup/hold time for flipflop's reset. On the other hand, SDF file generated by designcompiler does specify that. Does anyone know how to fix this? Thanks
Hey, guys, I have written a tcl script to drive DC to uniquify a design. But I always get an error said: Error: File is not a DB file. (DB-1). How to solve this problem? Can anyone help me? Thanks.
Hi, If I specify a net in a verilog module, is it possible to find the primary inputs and path to the specified nets in either PrimeTime or designcompiler? Thanks, Anand
Hello, everyone: We encountered a problem on specifying clock signals in designcompiler (DC) for synthesis. Our RTL design is fully synchronous, triggered by only one input clock. For some reasons, we have to partition the design into a number of blocks, and to synthesize each block with a local clock. All the local clocks are the same in fre
I'm beginner of using Design compiler (Synopsys) but I want to know the library file ,such as lsi_10k .db , class.db, gtech.db. which company serves this library or which nanometer they are served. though I looked for this data in solvnet, and also throw a question via e-mails, but They didn't give a clear answer. How can I get this inform
There is a IEEE (not Synopsys) standard for UPF IEEE 1801™ Standard for Design and Verification of Low-Power Integrated Circuits, the Unified Power Format (UPF) So, different tools of different vendors may support it. For example, from Synopsys, it can be read by VCS (with MVSIM), MVRC, designcompiler, IC Compiler, Formlity, PrimeTime, Prim
PowerCompiler (or designcompiler, as PC does not have own interface) may insert isolators, level shifters, always-on buffers, retention registers during synthesis. power gating cells are inserted after synthesis by PnR tool (like Synopsys IC Compiler).
Hello everyone, I did a synthesis of my design with the Design Compiler and Formality signals me that all compare points are equal (*.ddc vs. RTL). Also its possible to read back the ddc file with DesignVision and generate some schematics. But when I read my design into Primetime by typing: read_ddc xxx.ddc link_design The
So, what's the "pre-placement synthesis" and why it's needed? If you are using Synopsys designcompiler (for example) without topographical mode, it is pre-placement synthesis. In topographical mode, it will synthesize netlist and optimize it for some kind of placement. The pre-placement synthesis is faster and does n
Hi, I met a problem while I put test points with designcompiler. This chip has 5 bit mode pins. Each mode corresponds to one operation mode, such as FUNCTION_MODE/SCAN_TMODE/BIST_TMODE/JTAG_MODE/.... The hierarchy is, - top_design (port: PGPx, ...) -------- PAD -------- core ---------------- gpio (pin: o_SCLK) -----------------------
Dear engineer people I 'd like to get your advice. With Virsim, I wanted to simulate my gate-level netlist synthesized by designcompiler. With the synthesized netlist and library file, I used virsim. However, I couldn't simulate because the library file (~~~.lib) is Asic standard cell library; It is not a verilog-format library. How ca
You mean simulation by using Modelsim and synthesis by using designcompiler. If you write your code in a standard manner, you will not have major problems. I recommend you to write your code in a standard way in which you separate combinational and sequential parts based on Huff-man model of a digital design. By the way, timing verifiation is the
I have generated a DFT ready gate_level netlist, with TestMode connected to "Dummy 0 Clip Cell". When TestMode = 1, the negedge clocked F.F. is changed to posedge clocked F.F., a clock mux is used. When I analysis timing, PrimeTime knows the F.F. is negedge, but designcompiler does not know it, and I must do set_case_analysis to get the corr
hi, powercompile is included in designcompiler, you just need a license feature to use it .