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I made a netlist of single ended diff amp but I am not getting right curve between input differential voltage and drain currents of differential pair mosfet M1 and M2. Can anyone tell me where I am wrong... .title'differential amplifier' .option acount=0 default acount=1 Vdd 6 0 DC (...)
1) what are your voltages? Supply, input, output. 2) You tell us p-p voltage, but what's common-mode voltage? You might be pinned up against your power supply rail. 3) HOW are you adjusting your gain? In the diff amp? In the second stage? 4) what is your frequency? AC coupling is not going to work very well below some frequency.
135454 135455 1)Most opamp use nmos differential amp, but this one uses pmos. why? nmos is faster. 2)the third stage, buffer stage gain, and on the circuit, it shows 2 pmos(m8, m9). why? isn't it inverter is used as buffer? how's 2 pmos is a buffer?
Any papers about this issue: high supply voltage but low voltage input diff pair is used in order to reduce size and to improve the matching issue. Thanks.
128912 1)first stage of 2 series diff amp. It says its level shifting. What level does shift from and to? 2)at the output stage, two inverter with their output tied together. What's purpose of that?
When i am doing slew rate analysis for a fully differential amlfier, at the output , i am not getting a proper rising or falling pulse, it's rising , falling and again rising. i tried to slove it by increasing the gain and UGB of CMFB, but it's not working. But by removing CMFB its proper. How the CMFB affects the slew rate of a fully differential
Below is a diff amp I am planning to use to read value from a capacitor. I will be using a saw tooth reference voltage and output will be high when vref>Vin else low. Problem is my input voltage is negative dc voltage. Can you suggest me how to change my circuit? .param + Lch = 500n + Wnsa = 300n + Wpsa = 300n [
Hi, would someone help me in understanding the inverting and non-inverting nodes of the following schematic? The input differential stage has an active current mirror, node 2 and 3 are the input nodes. node 2 has an DC+AC signal and node 3 is a pure DC signal as Vbias. I am trying to find out which node is the inverting node and which one is the
Hello! After simulate this simple amp (all properly biased), I simulated the graph on the right hand side: Looks like for the low freqs, it's got a PSR of 0dB (ac disturbance in supply, measuring ac at the output). Isn't that weird? Doesn't 0dBs mean that transistor 3 acts as a resistor? Can someone explain to me the theory behind that? Could
I'm trying to design a fully differential IF amplifier in 0.5um On semi process, and its input referred noise voltage is going to be critical in the system's overall performance. The source impedance is low, in the range of 50-1000 ohms, so to keep NF<3dB I'll need vg on the order of 1-2nV/√Hz. The operating frequency range is around 200kHz-2
I am looking at building a Pre-amp that has a high impedance due to having a high impedance load (Like that of most Piezoelectric Elements). My biggest issue with this is that it needs to feed an ADC that is unipolar but can be either single ended or differential. The circuit also requires bandwidth from 10Hz to about 5-10 MHz. I'm working with
Hi guys. I have to design the layout of the above mentioned ota. I am thinking on how layout the ota amp. This OTA has PMOS input transistor. What I was thinking to do was to follow the schematic. That is: Interdigitize the cascode transistores that bias the diff. pair. Interdgtz the differential pair. Interdgtz the current (...)
Hi, Is there way in system Verilog to compare line by line two files(its not know whether file will have strings or digit so no %s, %d ) Can I call $system in SV to do diff in Questa Sim or Is there any best way to do it like tcl command etc ? Thanks, GSB
Hi, I need to sense a differential voltage of 2000mV and the source is very noisy. I think to use a Intrumentation amplifier, but I have two limits. The first is the supply voltage, I have 12V or less and 0V, not negative voltage. And the second one, is that I need to read this voltage with a DSP(3.3V). I though to add a 1.65V offset voltage
I have designed 5MHz bw 2stage CMFB diff amp. but i could not adjust the Phase Margin using R,C values for the compensation, in my case when i achive PM = 60 , bw reduces to 800kHz. is there any method to compensate this amp of BW 5M or 3MHz with enough PM. Regards, Safiya
Hi I need help with a relatively simple Analog design problem.... I have a differential signal that I am 'tapping' into. (It goes to another input impedance of my circuit must be high > 100kR). The characteristics of the signal are: amplitude can be 1vpp to 5vpp Offset is always positive (and the signal never goes negat
Dear all, can anyone explained me diff between voltage optimiser & voltage stabiliser. peaple giving optimiser effieciency over 95 percent while stabiliser is able to give only 80%.. what is special mechanism used..?? to increase the efficiency. if anyone knows lings pls mail
I am working on a highly linear differential amplifier design using cadence. please suggest the issue that must keep in mind while designing linear system
Hi, can any body tell what is the difference between micro controller & microprocessor. Is the processor present in smart phones are micro controllers or microprocessors. tell me whether the pc & cell phones are called as embedded systems.
Hi, can anybody tell what is the difference between reset & restart in a microcontroller. please explain in brief.


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