Search Engine

41 Threads found on Differential Slew Rate
Can anyone help me with the hspice code for finding parameters like CMRR,GAIN,OFFSET VOLTAGE,slew rate,FREQUENCY RESPONSE for cmos differential amplifier
When i am doing slew rate analysis for a fully differential amlfier, at the output , i am not getting a proper rising or falling pulse, it's rising , falling and again rising. i tried to slove it by increasing the gain and UGB of CMFB, but it's not working. But by removing CMFB its proper. How the CMFB affects the slew (...)
Hello guys, I am very interested in modeling a fully differential opamp with GBW, Gain and SR limitations, to analyze a 2nd-order SDM. I found the following post very helpful in this case: Besides that, the slew-rate is not implemented, and I tried to do it, but had no changes in simulation values. I tried to slew the (...)
I wanted to know that why do we go for differential pair input as compared to the pseudo pseudo differential pair??? I know from various discussions that my common mode rejection will be poor in pseudo differential but I wanted to know the comparison w.r.t other parameters like slew rate and settling time (...)
Hello all, I am designing a differential amplifier. I have read definitions about gain, gain bandwidth, slew rate, ICMR, OCMR and Phase Margin, but which value of these specifications are desired for a common differential amplifier? (For example: gain should be 60dB or 80 dB?) Thanks for any help in advance.
Hi all I am simulating slew rate of fully op amp. I set up as the way in picture below and simulatiion look ok, but I have a question about resistors value in simulation. How to decide value of resistor value? If R too large the current from vin to input of opamp will be 0 ---> the set up become ideal case (vin = vin_opamp = vout_opamp)? Thanks
Hello all, I am learning from books about two stage differential CMOS amplifiers and I'v designed one of them (see please the figure). Now I want to find out its : - SR (slew rate), - setting time and as well - ICMR/OCMR (input/output common Mod range), but I don't know how can I simulate it to get the specifications (...)
Hi!, We have just designed a 2 stage OTA with a cascoded differential pair as the first stage and a common source amplifier as the second stage. The gain is 59.3dB and we need to measure the slew rate. Can anyone please tell me how to go about measuring the slew rate? The method that we were using is (...)
Hi, i've designed a CMOS folded cascode opamp to have a slew rate of 150 V/us (Iss of the differential pair is 30 uA and CL = 200 fF) in unity gain configuration. I found that ICL is about 1 mA.I saw current in the differential pair is unbalanced in one branch only for a very quick time so the capacitor can't charge like i (...)
I have used two out of phase pulse inputs with the opamp configured in unity gain configuration as in the attached picture. where all R's=1K,then i plotted vout1-vout2 and taken the slope of it,which gives a value of 3e10,it gives almost the same value when i calculate it with delta cursor.Does it mean a slew rate of 30000V/us? or should i connect
Most probably you are experiencing slew rate limitation in the amplifier. This would explain why you see reduction in the output amplitudes when you increase the input. Do you see distortion in the output sine wave? Check the current in the input differential transistors and see if at the peaks of the input signal one of the (...)
How to calculate slew rate for differential folded cascode cadence can anybody tell me ....?? thanks in advance...:smile:
I am doing the project on Modified Nauta configuration using double CMOS pair. Plz help me how to calculate slew rate, PSRR, "dc tran ac" for gain, CMRR. And plz tell me the mathematical analysis for this configuration to above parameters and differential output transconductance and common mode output transconductance.
Hello guys, How can I cancel the offset produced by transistor mismatches (monte carlo analysis) to measure the slew rate (trans analysis)? I want the offset to be cancelled for each iteration of the monte carlo analysis, but of course i cannot calculate the input-referred offset... it's different for each iteration and random. Is it possible
With a folded cascode of the first stage and common source as the second stage. How to calculate the slew rate? The value I calculated by Itail/Cc, that is the tail current of the differential divided by compensation capacitance, is far different than the one I simulated. Should we consider the miller effect here? It seems the variance (...)
Hello all, Regarding measuring slew rate of single ended opamp its easy and straightforward, by giving a step on positive input and using the opamp in the follower configuration. But i was thinking how would i measure for a fully differential configuration Thanks and look forward for some replies!
Hello all, Regarding measuring slew rate of single ended opamp its easy and straightforward, by giving a step on positive input and using opamp a follower. But i was thinking how would it be for a fully differential case? Thanks and look forward for some replies!
Dear all, I want to know the effect of dc-gain, ugbw and slew rate in 2-1 MASH sigma-delta modulator. How to model fully differential opamp by using Verilog-A?
A fully differential opamp could be connected in a single ended unity gain configuration. That mean that the positive output is only connected to the negative, sometimes called inverting, input. Test signal is driven into the positive input. But that could give sligtly different slew rates. I opt for applying an unity gain inverting (...)
I have designed a fully differential op amp. I do not know exactly how to measure the slew rate for a fully differential op amp. Generally for a single ended op amp we connect the op amp in non inverting(feed back) mode and measure the slew rate. How to measure the slew (...)