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39 Threads found on edaboard.com: Digital Asynchronous
Hi nwo4life, It seems, that you have pretty little experience with digital ICs? Well, everyone has to start from the beginning. As I assume, that this the very beginning for you, I'll give some generic hints and advice on quite a basic level: MM74C90 is a CMOS asynchronous decade counter. This particular family is quite old, and has a wide op
Also, see section: "HANDSHAKING AND FIFOs" in: "Crossing the abyss: asynchronous signals in a synchronous world" at: Regards, IanP Handshaking allows digital circuits to effectively communicate with each other when the response time of one or both circuits is unpredictable.[/quote
Latches should be avoided in digital designs because they cause timing related problems. Latches do not have clock signals and thus will increase the combination delay of the entire logic. Latches can also lead to unwanted outputs by changing the logic at times. Designs with latches tend to become asynchronous and this causes timing related problem
Hi, Get some good book about digital design or logic syntheses. Look for Moore and Mealy tip of state machine.
How it is useful in digital design? any advantages over normal FF? The advantage of asynchronous clear is this: the initial state can be set even if there is no clock. This is useful in many situations. For example, suppose the FF is controlling a solenoid and the FF, in turn, is controlled by a cpu. You
complete latch based design is possible, but it will require multiphase clock. best regards Is it possible to do a complete latch based digital design for an ASIC ??
digital logic for SAR is not so complex, and the best way is to do it by yourself with D-FF with asynchronous reset. You have such schematics in books. Only you need to adjust your start and stop signals. If somebody else writes vhdl code for you, you will need additional time. If you write as analog designer you will always suspect
latch will not ne clocked a flip flop is always clocked. good book to start basic digital electronics is : Mauris Mano
i can suggest some books that cover these topics. asynchronous Circuits using asynchronous SEQUENTIAL CIRCUIT DESIGN from digital DESIGN by MORRIS MANO PERIPHERALS AND INTERFACING OF 8051 Typical Bus structure ? Bus ? memory organization ? Timing characteristics ? Extended Model and Memory Interfacing ? Polling ? Interfacing (...)
hi everyone, Qn(a): How does a digital phase lock loop function? Qn(b): Can a digital phase lock loop be used be used to synchronize asynchronous data with the clock? If yes, how? thanks
yes i have seen this classification in barkey course ee241 advanced digital integrated circuits
Hi All I'm Moorthi and I'd be thankful if my following query is answered. I'm in the process of design and development of effcient method for symbol timing recovery for data rates greater than 512Kbps and upto 32Mbps. I'd like to implement the method which is not using PLL or DPLL. The idea is to use constant sampling rate at the receiver and
I am agree with you about the asynchronous circuit will play a great role in the future's digital design. but i think that the synchronous circuit will still the most important methods in future even thought more powerful synthesis eda tools can be used for asynchronous circuits . because man is always favour to a easy design methods and (...)
Hi, Nothing is stable in the real world. You need to think about all kind of noises in your design, especially with mechanical sensors. So if you want stable signal you need some kind of deglitcherizer. If you use asynchronous signal you to deglitcherize your signal with synchronuos digital circuit or with simple RC circuit. With RC circu
1. What is setup/hold time and metastability? 2. How to interconnect two synchronous digital design with different clock domains? or How to connect asynchronous external signal to synchronous design? 3. What is DFT? (sometimes say Discrete Fourier Transformation :)). 4. Whal is logic race?
Perhaps a good book, like "digital Design", by John F. Wakerly, can help you. In this book you can read the following: For proper system operation, the hardware design of a state machine should ensure that it enters a known initial state on power-up. Most systems have a RESET signal that is asserted during power-up. If a state machine is buil
You may find several answers for what you need... 1) a simple way which simple guides you to the result... That's nothing more than making the state diagram and then using Carnaut tables take the function... 2) an analytical view point (found in M.Mano - digital Design - Prentice Hall) 3) an insight view point found on VLSI books i could su
Dear friends, I need your advice on a problem to which I'm working: I need to send 9 signals from one board to another. These are digital signals, asynchronous one to the other, with a pulse of about 100 ns every 1 ms or so. The application is supposed to use as less power and weight in the cabling as possible (it is intended for space use)
Designing Asynchrounous digital circuits is the forefront challenge in digital VLSI Design - and is the future for low-power, very high-speed organic based technologies. Nice links !