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39 Threads found on Digital Asynchronous
I wrote a frequency counter program in PICBASC PRO for 16F88. This is a pretty standard stuff: timer1 is an asynchronous counter and timer0 is a clock. When I run this counter in Proteus, everything is OK if I feed B6 timer1 pin with the digital clock signal (it works up to 100 MHZ). But when the signal is not digital clock, even if it (...)
Designing a very high frequency counter circuit is very difficult and you will end up with very low difference in digital values. Better try to construct a low frequency VCO with high variation in frequency. I think you can simply design a VCO using 555 or 565 IC(I already did that once).
Please provide a digital system or circuit to detect a pulse.
How to design the digital logic from the timing diagram
Hello, I need some assistance in writing the code for a time to digital converter with high resolution for an FPGA in verilog using delay carries. I haven't used verilog in a while so any help would be useful.
Write 5 applications using Timer1 1. asynchronous Clock Mode (read AN580) 2. Counter 3. Control the operation of electrical devices based on a programmed schedule (Simplest application is LED Blinking) 4. Delay (Timer Based) 5. digital Clock Write 5 applications using Timer 2 1. Color Sensor (using TCS230) 2. Delay (Timer Based) 3. Sonar Range fi
Hi guys. When designing an asynchronous digital design, can you tell why need two flipflop to synchronize the asynchronous reset ? Can we just use one flipflop to synchronize the asynchronous reset for the internal flipflop use ? Thanks!
Check a few circuits and tutorials 7.9 asynchronous (Ripple) Counters The 7493 IC Binary Counter 3-bit binary counter : digital INTEGRATED CIRCUITS [url=www
As long as you remember that using the pll to generate the clock for your ADC will potentially degrade your effective number of bits, the you should be fine. But looks like you have a clean 80 MHz clock already, and want to use the PLL to generate fpga internal clocks for digital part.
Hello, Can someone help me in designing an asynchronous counter using orCAD tool? It has to be able count from 1 to 100 and back down to 1 depending on the input. Thanks
I have been trying to figure out the best way to decode a tricky signal (A multi-level digital signal with random pulse widths) on 4 parallel lines. The output should be a 4 bit digital code - I figure instead of decoding each signal with a separate ADC I can decode all 4 signals at once by just detecting signal transitions (represented by tran
Dear all, How to design a FIFO for taking two ASI inputs.Experts please tell me the flow. Thank's Sushant.M
what is critical path analysis and false path analysis? why it is required? suggest some books to study this.
Hi, I have asynchronous wrapper (spice netlist annotated). This comonent have a lot of I/O and Spectre simulation is very complex because I fed inputs with vsources for digital simulation. There is a lot of inputs and the signals are very complex to generate using Vpulse. Also simulation last 10 Hrs !!! How can I use VHDL testbench conta
Check the digital logic book of Brown and Vranesic book.
The source code is there in the Text book digital design using VHDL by Brown and Vrensic u can go thorugh that
pratibha m d, What is an async flip-flop in vhdl/verilog? A flip-flop is what actually makes a design synchronous since it is a clocked element. Other digital circuits such as and, or, xor, and muxes are async devices but flops and counters change on clock edges and capture the state of the other async devices. You might want to pick up a
Hi All, When designing a digital block with asynchronous reset, should this reset be buffered? Some of the standard templates (for sdc) seems to have the reset port as an ideal_driver and path disabled. If this is the case, wouldn't the reset pin be overloaded? Currently I have set the external_driver and load constraints on the asynch rese
Do you mean All digital PLL ?
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