278 Threads found on edaboard.com: Digital Pll
does anybody have experience in designing a digital pll in simulink. I am new to this stuff and need some resources to study about the method.
Analog Circuit Design :: 03-08-2017 15:29 :: hanikapa :: Replies: 0 :: Views: 338
I am using altera IP core pll with the setup shown in the image.
When I check the waveform in the scope, I have got a sine wave of 2 vpp with a DC component of 1.5 v. The issue here is that am using that clock to sync with the Audio codec WM8731 for I2S communication but it seems that the codec is not un
PLD, SPLD, GAL, CPLD, FPGA Design :: 03-03-2017 21:41 :: JulianCas :: Replies: 7 :: Views: 886
In most ICs I encounter, plls are present. But I don't know actually what's the use of it. Some registers are associated with it which you need to program. May I know what's the use of this pll and why are the registers need to be configured?
I know how pll works. It takes 2 input frequencies, one is from a crystal oscillator which is (...)
Digital communication :: 01-20-2017 06:19 :: ReubenMijares :: Replies: 3 :: Views: 854
If you have implemented an all digital pll, you have the angle information available.
Microcontrollers :: 01-05-2017 12:27 :: FvM :: Replies: 1 :: Views: 466
We are getting the current from Charge pump and then we converted it into voltage and the again into current. What is the use of this procedure. Are there any advantages.
Normally a digital pll has a phase comparator and an integrator with lead/lag compensation RC network to drive the VCO.
Using a charge pump
Analog Circuit Design :: 08-27-2016 21:00 :: SunnySkyguy :: Replies: 3 :: Views: 612
Hi, I am trying to find examples of TDC used in CDRs for use between the phase detectors and digital loop filter. Thus far I could only find TDC for use in frequency acquisition in plls, and nothing really for CDRs. A large number of TDC circuits I found for pll use the lower-speed reference clock as a sampler, but that option is not (...)
Analog Circuit Design :: 08-21-2016 21:49 :: ngox :: Replies: 0 :: Views: 578
Research about "all digital pll".
Circuit is simple, connect input signal to ADC input. Other option to convert sine to square wave and process with digital input.
Microcontrollers :: 07-15-2016 08:27 :: FvM :: Replies: 3 :: Views: 409
What is meant by acquisition range of pll?
How does it depend on loop bandwidth?
When we work on discrete pll domain, how does it affect the acquisition range?
I am currently working on timing recovery design of digital receiver. One of the specification is given as Acquisition range should be 10% of Symbol rate. From this information, (...)
Digital communication :: 06-04-2016 10:54 :: avishek_sinha_roy :: Replies: 0 :: Views: 529
A standard solution uses an all-digital pll with the grid voltage as reference, comprised of ADC, multiplier phase detector, PI loop filter, NCO with sine table. To generate the sine pwm, the NCO signal has to be multiplied with a factor to adjust the output to the actual grid voltage, usually driven by a current/power control loop.
Microcontrollers :: 02-20-2016 09:44 :: FvM :: Replies: 4 :: Views: 1201
I would like some resources on the topic of "All digital Phase Locked Loop", if you recommend a good book on the subject or some papers or even lectures.
I am also interested in the FPGA implementation of the ADpll, any recommendations or tips are appreciated.
Thanks in advance.
Digital Signal Processing :: 01-20-2016 13:35 :: ammar_kurd :: Replies: 2 :: Views: 763
I'm looking for ideas on where to start designing a circuit to send serial data between a set of uC's (Arduino & Raspberry Pi). I need to encode data, transmit it on top of a 24VAC/60hz wire, and decode it at the other end. The data is digital -- speeds around 19,200 baud or better would be ideal.
I was considering:
Using a single pll on a ch
Digital communication :: 05-12-2015 16:18 :: quantboy :: Replies: 0 :: Views: 794
When doing a pll Phase noise analysis, I know reference noise within the loop BW is enhanced 20 log N, but in a digital pll with a PFD, when the mfg supplies the noise floor or figure of merit, is the PN within the loop BW (enhanced) simply added to the phase detector noise, or is the phase detector noise also enhanced by 20*log N? Thanks (...)
RF, Microwave, Antennas and Optics :: 03-14-2015 12:40 :: 4Ceesuns :: Replies: 1 :: Views: 696
I am designing an ADpll but am not getting which phase detector to use.
EXOR gate phase detector
JK Flip-flop phase detector
digital phase frequency detector
moreover there remains a TDC along with it , but some papers tell that TDC alone is sufficient.
please help me understand what should be the preferred choice.
PLD, SPLD, GAL, CPLD, FPGA Design :: 03-14-2015 20:00 :: jubin007 :: Replies: 2 :: Views: 711
I have some experience with digital pll. However, I am completely new all digital pll. I am looking for a practical design book on all digital pll. Any recommendation?
Digital Signal Processing :: 12-06-2014 08:14 :: oucd :: Replies: 1 :: Views: 1022
pll's have many purposes for scaling up or down , fractions, digital clocks, RF clocks, time of day clocks.
Crystals are chosen when the design has a need for tight specifications but lowest cost.
Otherwise TCXO's are very accurate (<2 ppm) and easy to use.
Voltage, stability and temperature requirements are mandatory when making any choice. Vol
Analog Circuit Design :: 02-23-2015 18:49 :: SunnySkyguy :: Replies: 3 :: Views: 580
There are numerous text books on the topic but I assume you need/want hands-on :) Why not d/l the free software from Analog Devices Simpll. You can play with all sorts of settings and get a feeling for what happens when you alter loop filter vs. switching time and spur supression.
If you really want to read some basic stuff, digital pll (...)
RF, Microwave, Antennas and Optics :: 06-16-2014 21:09 :: webdog :: Replies: 9 :: Views: 1458
In an all digital pll with a NCO how exactly can you expect the generated sine wave track the input sine wave? I've been working on one using atan Q / I computed every millisec. It will track frequency if it starts out close enough but there are clear cycle slips on the oscilliscope. I've also tried another pfd thst tracks risig edges to determine
Digital Signal Processing :: 06-15-2014 15:19 :: JHEnt :: Replies: 0 :: Views: 673
Anyone worked on digital pll ? I want to make a design on it but without using any kind of analog circuit. I though about this and may be I need to design clock multiplier and divider to generate a desired clock frequency by reference clock.
If anyone have any document or link .. please let me know.
ASIC Design Methodologies and Tools (Digital) :: 05-23-2014 09:38 :: rahul.achates :: Replies: 0 :: Views: 652
That device is a digital output (CMOS), not a sine-wave.
How are you measuring your output?
If you need your "output to be 12.8MHz", why do you need a VCO? If you really need a VCO, what's your frequency range? Accuracy?
Analog Circuit Design :: 04-09-2014 13:20 :: barry :: Replies: 2 :: Views: 606
i want to make a software pll using DSP controller...i have googled a lot and found many links but mostly are in paper form i.e. they describe the conversion from analog to digital and the transfer functions of that...
i am more of a controller guy so dont know how to implement them on controller......
if anyone has experience in designing softwa
Microcontrollers :: 04-06-2014 18:52 :: patelvivekv1993 :: Replies: 0 :: Views: 517