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56 Threads found on edaboard.com: Digital Time Delay
Hi , or Hi Mr. Peter (tpetar), I have PIC18F45k22 with DAC MCP4922, I need to design a feedback controller for my INverter 12V Dc to out put of max 9v peak AC 50Hz, sinewave, I use LC filters and at the output to make read by PICMICROPIC 18f45k22 at AN2 channel , I use feedback gain of =0.1 and a noninverting level shifter my circuit I a
Hello, sorry if this is a bit vague, but could anyone give me some tips on how to implement a TDC (based on tapped delay structure) in Simulink. There seems to be very little information online on how to simulate such a device in Simulink. I need it for simulation of an All-digital Phase Locked Loop.
There's no general solution without considerable restrictions of voltage and frequency range. You can't directly create a phase shift for a time domain waveform, you have to measure the pulse period and calculate a time shift. A digital delay of the sampled waveform might be the most simple way. Practically, use a (...)
Hello, I need some assistance in writing the code for a time to digital converter with high resolution for an FPGA in verilog using delay carries. I haven't used verilog in a while so any help would be useful.
In Synchronous digital design, signals are sampled and changed at the clock edge. If a signal change at the clock edge, doesn't the register receiving this signal violate the hold time because the signal changes shortly after the clock edge?Is c to q delay + propagation generally greater than the hold time or do we have to d
Hello every one, Please help me in understanding of digital cicuit design. What are the factors should be considered while designing a Board particularly for Communication protocol. For example time delay of ICS etc., Please send me the link if any, Thanking you, Regards, Bhagavan
Analog audio delay chips for ms delays have been previously manufactured, based on CCD structures. They have been superseded by digital signal processing since 10 or 20 years. Audio delay in a microsecond order of magnitude can be achieved by a few LC stages.
Hi, Well done, its always great to see things start for the first time. Cannot help with the C code detail, but most of the Ports default to Analogue Inputs at power on, suggest you turn then to digital before making them Outputs using ANSEL
HI I am using AD7705 for Analog to digital conversion in my is 16 bit resolution,2 channel,8 input,Sigma-Delta Configuration ADC.I am having doubt that how much time(in ms)it will take to change from one channel to another channel (CH 1 to CH 2) or vice versa.Can you please explain with its calculation....
Hi, I am doing a digital timer using AT89C4051 and DS1307 RTC. time is displayed on 16x2 LCD. I have enabled 1 HZ square wave output and updating the time on LCD every rising edge. The problem i am facing is the RTC time is not accurate. For every 24 hours i observed a delay of 2 (...)
I can't really help you with proving whatever you're looking to prove, but I can say that minimum average delay is not necessarily what you care most about, in designing a high performance digital circuit. I've spent a lot of time tweaking logic gates' N and P widths to get the -critical- transition where it needs to be, and averages don't (...)
Hello, For testing purposes, we' ll need to show some kind of a time delay between RF and LVDS signals on different lines. Can this be done on oscilloscope(a 4-channel digital Phosphor Oscilloscope) without any unforeseeable impact on time characteristics or would I need any type of LVDS-something conversion[/B
Can someone please describe the effect of input delay and output delay on the maximum operating frequency of a circuit ? I knew that max operating frequency of a given digital circuit depends on Tclktoq of launching flop + net delay + combo delay + setup time of receiving flop +/- clock (...)
ECL is fastest among the three because the transistors are used in difference amplifier configuration, in which they are never driven into saturation and thereby the storage time is eliminated. The digital logic family which has the lowest propagation delay time is ECL (Lowest propagation delay (...)
Have you got a delay line between the audio input and the noise gate? Points to a basic dilemma. A classical analog noise gate has no option to implement a delay line with acceptable signal quality. If you think about a state-of-the-art digital delay, you'll end up with a fully digital effect processor. (...)
making a digital clock using DS12887 and at89c52. I just wrote time reading and displaying code... i wanted to display on 7-segment(comon cathode) using BCD decoders(4511). i test my circuit for seconds..they are working fine but for minutes and hours,it is malfunctioning on displays...(schem
Hello all, I want to carry out an experiment which consists of "operating" a digital TV channel in the UHF band in order to remove/add contents. The DTV channel is 64QAM, 8MHz bandwidth, 8K subcarriers. After de decoder, the DSP/FPGA will deal with the streams, and then will be encoded again: Will anyone expect an appreciable delayed effect in
Possible yes, but limited in terms of signal bandwith and dynamic. Assuming you mean an analog signal, the best way is most likely by digital processing. Previously, magnetic tape loops have been used for delays in the seconds range.
"a fraction of a second" seems a correct timescale for mechanical relay circuits. digital logic possibly needs a few 10 ns of delay (of course a nanosecond is also a fraction of a second...).
hello all,i faced an interview yesterday and was stuck with one particular question of digital design. the question is as design a Combinational logic which takes a train of pulses with different pulse width (1ns - 5ns) and produces pulses of only 5ns as should discard pulse widths less than 5ns. help appreciated. i have attached a