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52 Threads found on Dracula Lvs
Where - i.e. from which tool - didn't you get correct results? Simulation, layout creation, or dracula lvs? May be the used tool doesn't (yet) know - or cannot assign - these Finfet parameters.
Dear all, After i ran , it displayed that: */N* AT STAGE: 33 ******************************************************************************* */N* lvsCHM (REV. IC6.1.5.08-2010 / LINUX /GENDATE: 30-AUG/2010) *** ( Copyright 2010, Cadence ) *** */N* EXEC TIME = 13:55:53 DATE = 1-J
Hello, I came across these names Assura, dracula, Calibre, Hercules. what is the difference between them? it got me confuse. most of the time i use calibre for DRC and lvs verficication, but sometimes assura is also used. they are also for DRC, lvs and parasitic extraction.... the difference is that, they are produced
Use dracula or Assura
As for lvs check, when there are floating ports in schemetic, and layout miss thoes ports, dracula will report all the missing ports name. While Calibre only reports how many ports unmatched. Could anyone tell me how to make Calibre list all the name of the floating ports missing in layout? Thanks.
Hi all, I urgently need some advices on this matter. I used Virtuoso layout editor to draw some circuit. I need to perform lvs with dracula. Could anyone show me how to set up connections, like VDD, VSS, IN, OUT, in Virtuoso etc.. so that dracula can recognize these. I use "Create > Pins " menu from Cadence, and in the Connectivity (...)
What about dracula? In SUSE 10.2 amost all Cadence tools are workable except Pdracula for lvs check, LOGlvs and DRC chek are OK. For lvs I got an error message: unrecognized symbol gdm_open()
hi ther, looks like i need to work with dracula finally ;-) i have no clue about this tool. i nver worked on it. i was wondering if ther is a way i can convert a dracula rule deck to calibre rule deck. any one ever did such a thing ther? cheers pvnk
The text name must comply with the layer the verification tools uses to regognise pins. For cadence virtuoso .35u tsmc tech. For example we use dracula and Hercules and the lvs text layer is met1-Dr. and met2-Dr etc. Adding the same as pin layer wont do a thing, as you are just putting met1 on-top of met1, if you merged them it would disa
How to see device parameters in layout about dracula lvs? such as diva , it can see the device be extracted in layout in dracula lvs , can I see the mosfet W(width) , L(length) be elemented or extracted in layout ?
Change 30M to 30e6. I also had problem with shorten resistors before. It seems a bug for some dracula version. I thought M is recognized as m. But it doesn't explain why changing 30M to 20M fixes this problem. So now I have some doubts about my explanation of that
export CDL : but our schematic involve in parameter cell ,such as inverter we want to get the netlist : XI0 Y A inverter WP=1u WN=0.5u LP=0.18u LN=0.18u but the WP WN LP LN are missing XI0 Y A inverter How can I do? thanks
What lvs tool do you use? If it is dracula there is should be lvsCHK command that defines a lot of options how to treat parallel devices.
we use dracula verify layout. there is a question. mix-signal chip has two gnd --------agnd dgnd, they are both connecting subsrate. I give two substrate for nmos-------------- pwell , psub. element MOS ngate nsd pwell element MOS ngate nsd psub or element MOS ngate1 nsd pwell ele
for dracula lvs , I stream out CDL. but the *.cdl has not the parameter m of mosfet. How can I do? thanks in advance
I have rundrc.dat and runlvs.dat in UNIX Solaris. I can run DRC and lvs ok, but I can't use rundrc.dat and runlvs.dat to run DRC&lvs in LINUX. What should I do to run DRC&lvs in LINUX? Help me, please! Thanks.
I have some diva rules which including drc, lvs & lpe, is there any way to transfer them to dracula format? It's troubled to transfer them by hand since there're two thousand lines. Thanks for your help! B.R. Joffre
Hi,all How does dracual lvs extract channel width and length of MOS in layout? I mean how the "W=** L=**" expression is obtained by dracula lvs run. This expression is locating on the right side(layout devices, nodes and parameters) of .lvs file? and, if i want to change the formula for calculating the value of W or L, (...)
How does dracual lvs extract channel width and length of MOS in layout? and, if i want to change the formula for calculating the value of W or L, what should i do? It is always easy for calibre lvs users to find the expression and revise. Thanks in advance
Hi All, I am using Tanner L-Edit for Layouts and Cadence's dracula for the verification. Can anybody can help me out in how to interface the dracula with Tanner. Tanner works in Windows & dracula in Linux. Pls if any body can provide me the detailed step by step procedure on verifiying (DRC, lvs) the Tanner (...)