Search Engine www.edaboard.com

Drc Ams

Add Question

Are you looking for?:
and ams , verilog ams , ams setup , cadence and ams
22 Threads found on edaboard.com: Drc Ams
HI I have a problem with virtuoso and ams 0.35 I insert a pmos but I always receive the same error and I do not know how to fix it I puts a pmos for the library 136066 De assura drc indicates BAD_SUBSTR_SUBTAP_FLOAT_ERC but I think the substrate is well fed to VDD thanks.
Hi there, I'm making an OTA layout in Cadence, ams 0.18um (cmhv7sf). The only drc error I have is about I/O wirebond - it says that some transistors don't have body contact while there are n-well contacts. When there where contacts on the left and right side errors where the same. 133931133932
Hello there, I have drc error which says nwell is hot,though the nwell is connected to vdd!. I am not able to understand why I am getting this error. Any help regarding this is greatly appreciated. I have attached the layout screen shot for your reference. Thanks in advance, 110026
Hi everybody: I am using ams H35 tech for HV-Processor M0 Chip. The P&R and drc have passed. Now I am using Assura to do LVS and encounter some wired problems. Who has some ideals? thanks and regards Error: Device 'cds_thru(Generic)' on schematic is unbound to any layout device Device 'RDIFFP3(RES)' on Layout is unbound to any Schematic de
Hello all, I have 2 drc errors that i do not understand in my layout. I am actually routing a very simple inverter but using a HV NMOS, with a protective diode on the bulk. And since the layout of this transistor do not looks like the one we have usually when we use a common HV MOS, i am a bit confused. Here are the 2 messages i do not unders
Hi all; I am working with ams H18, it is same with IBM HV 7SF. In the floating gates drc (Antenna Rule) check, I get the following error message: "Gates over RXHV touching MT touching FT/FTBAR must be tied down by MT metal." First what is the meaning of tie down? Second how can I achieve to tie down gates by MT metal? Third, when I us
Hello My circuit is a decoder. I have created the layout of the circuit. I am using assura ams H35. And i have already passed successfully from drc and LVS runs. The next step is to perform the parasitics' extraction and run post layout simulations. But when i perform the parasitic's extraction, I get this error ERROR (LBMI
Hi everyone, I am using ams 0.35um process.I am getting BAD_SUBSTR_SUBTAP_FLOAT_ERC error while running ASSURA.Please someone help me in debugging this error and how to solve this. Thanks
Dear All, When I run drc and LVS for my design, there is an error: Error while compiling rules file /home/user/amsc35/calibre/c35b4/c35b4c3.rules: Error POLYNET1 on line 1738 of $ams_DIR/calibre/c35b4/cac35b4rules_all.run - the POLYNET operation is obsolete. Please use CONNECT or other alternative or contact Mentor Graphics for (...)
Hi, Your prb is an ERC and not a drc probkem.
Hi All, May I know how to enable dynamic drc and dynamic measurement during layout. I am using ams C35 process on Cadence and it uses DIVA for layout verifications. Thanks a lot in advacne!! M.
I am having problems with the final layout of my chip. In the case of individual blocks, I am not getting any errors from drc and LVS. At LVS of the chip, I get errors regarding more gnd connection in the layout rather than in the schematic. I have heard that routing over poly capacitors is not allowed. I am using ams (0.35 um) technology. Secon
Hi gurus, I am trying to do a simple inverter layout, when i run drc i am bugged by this drc error of Info: hot nwell. vdd! is labelled on to the M1, so thats not the mistake i have done ! I dont have any clue absolutely how to solve, Any help is highly appreciated. Regards, santini
Hi folks, am designing a digital chip in ams .35u library. Inorder to reduce power I would like to used a scaled Vdd of 1.2 V instead of the 3.3V (nominal) specified by the vendor. The has been simulated correctly in Nanosim with the scaled Vdd. However I am unsure whether drc (esp transition)will be satisified. Pleas give ur comments. have a
Hi, it seams to be a bug in the calibre-drc rule file of the ams hit-kit. Which version of hit-kit, do you have installed? Maybe an update can solve the problem? Do you have the possibility to use assura drc to test, whether it is an bug in calibre? Regards hqqh
your hit kit is not properly setup. it can not see your drc file. hock
I was applied drc for one standard cell that will gives errors:Metal2 coverage must be larger than 30% entire chip and also will shows whole surface of cell as in circle.Please give the reply for that problem.Also gives to METAL2,6 for...coverage must be larger than 25% every 500*500um square.I am using Tanner tools,Hyper is for drc veri
Hello, all i uses a layout of a spiral from ams hit kit 0.35um technology which is designed and enclosed in the kit, The problem is: i uses diva for layout, when i do drc Check, the following statementis an error message: spiral_term contact does not connect to two layers any help please??? thanx in advance MohamedAbouzied
Hello, all i uses a layout of a spiral from ams hit kit 0.35um technology which is designed and enclosed in the kit, The problem is: i uses diva for layout, when i do drc Check, the following statementis an error message: spiral_term contact does not connect to two layers any help please??? thanx in advan
Sedit -> schematic tool like Cadence composer or workview viewdraw or ECS (ams/ADP) Tspice -> like hspice/tspice for ASIC design .. we use really aisc design tool not Tanner .. ledit can layout fully chip . but fab only support dracula or calibre LVS/drc command file , how to use Ledit is really ASIC design ?? Tanner be use f