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357 Threads found on Drc Error
Hello :) I designed a simple NAND Circuit and used it in Half adder circuit, and even though the nand layout had no drc errors when I used it I got 328 Edge not on grid error !!! and all of them was about my nand cell ! How can I solve this error in virtuoso i am using the simple Diva tool. Best Regards 126331[ATTACH=C
Hello all, I am layouting a block using TSMC65nm. I got a drc error which I don't know how to clean it. I was wondering if anyone has faced this error and knows how to clean it. Thank you. error: width > 0.3 um (W). (It is allowed to use one VIAx for a connection that is > 0.8 um (D) away from a metal plate (...)
Hi, your spacing between the pads is about 0.2mm. There is nothing obviously wrong with the package. I assume the drc setup says it needs more than 0.2mm spacing. Usually the PCB manufacturers have no problem down to 0.15mm. So i recommend to adjust the drc setup. Go to the PCB manufacturer´s website and look for design rules. Find the values
Pls help, I am doing the layout of a 12bit ADC. while connecting between the digital(3.3LvTr, connected to VDD 1.2V)and analog section(3.3lvTr, connected to AVD 3.3v), all the rules for 3.3v analog section transistors are flashing for the 1.2v digital connection. I have added an antenna diode to the analog gate which is connected to the digit
I was able to solve the above error and get 0 errors in drc but then wen i run LVS the netlists dont match between the extraction and schematic giving me few errors that no of nets dont match etc. But then wen i leave the above error like that without correcting it and when i run LVS then netlists match with (...)
Dear All i have design a transconductance amplifier. done with layout of it.. cleared drc and LVS and PEX. in PEX i m getting some warning. i m not able to understand those warning but because of these warning i m able to generate config view. i m attaching the error file
I'm a fresh man in analog IC design. when I run lvs in calibre, it says calibre lvs rule file compiling error: undefined layer name parameter -- metal 5, I don't know why. Besides, I have no runset files in this process. My drc rule file runs well.
I have some drc errors i can not understand. I was told there are some files that contain an explanation of each drc/LVS error. could anyone help me know where to find them or how to interpret the errors? the technology i am using is TSMC13rf Example: OD.DN.3 { @ {OD OR DOD} density across full chip (...)
I have drawn the layout checked drc and LVS while extracting the layout the reisitors are not getting extracted pls help this is the error showing in cadence viruoso Delete psf data in /root/simulation/PMOSTEST/spectre/schematic/psf. generate netlist... Begin Incremental Netlisting Jul 6 05:33:48 2015 WARNING (OSSHNL-160): Th
In 110nm tech while running drc for capacitor i am getting this error how can i rectify this "in n_well , poly 1 overlap n+ diffusion is not allow".
Hello, I created a layout of a not gate using Virtuoso Cadence layout tool. Then I did the drc check and fixed all errors and I extracted the layout. After that I went into the extracted layout to try to post simulate it using ADE L (Spectre) after setting up the Analysis and the outputs and the stimulus. However I am getting this (...)
Can u please tell how to remove drc error: PSUB_STAMPerrorMULT... what does this error mean....
After fixing almost all the drc errors, I'm still getting some clearance errors in AD7490 component. Could you help me solve this? 116966
Hi everyone, I am using IBM 130nm cmrf8sf PDK. I made a simple inverter and performed drc, LVS, PEX with Calibre. The drc and LVS work well, but there is a PEX error shown as follows: "error: Could not find pin mapping for terminal sub of cell (cmrf8sf devicepad symbol). It will remain unconnected." I don't quite (...)
Hi, I have an error of drc (calibre drc, ibm CMRF7SF pdk, Cadence IC615): GR131_top: All (Gates not over TG) must meet the ratio of AM metal area to {(PC over RX oxide area) + 10 x (diode diffusion area)} <=150. - I created a core layout. I pass drc of core layout. - I added the I/O Pads and the (...)
Hello! I need help to label the ports in my layout. I use mentor graphics and I use this address to label the ports: Add->Text on Ports... In the window than appear, a push OK and the name of the ports appears in the layout but when I run the drc, appear this error: Check GRText_M1 : Text is not allowed on design layers. I think than this err
hello, i'm new with analog design with this pack of ibm and i have a trouble that i can't solve. I'm doing a simple inverter with Mentor Graphics in this technology and in the schematic i put the subc for the NMOS, but i don't have a contact for the substrate of the PMOS, and when i do the drc, this is an error message that shows up, i prove to
I am not able to resolve the following drc error in a UMC65 design. L2.D Minimum L2 density cross full chip is 10% What is L2?
Hi, can someone explain me what is happening with PCB editor and this drc error, Line to SMD Pin Spacing (pictures attached)? Explanation: First, I route the USB_P trace, and no drc error is shown. Then, I don't know how, the USB_P trace was hidden, but drc error appears. 116538 (...)
While i was implementing my project,i'm getting a drc error. Full error(could not post in title bcoz of length constraint). error: Rule violation (REQP-61) ibufds_connects_I_active - IBUFDS /.../.u_ibufg_sys_clk pin I has an invalid driver c0_sys_clk_p_BUFG_inst The signal that he mentions c0_sys_clk_p is an i/p to my top