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357 Threads found on edaboard.com: Drc Error
Another option that would not involve redefinition of the overall drc could be draw the component footprint with a biggest size that supposed, ensuring a margin of error.
Hi guys, Normally my friend will use ripup and route to connect those error line after the autorouting for reducing the error after drc. Is there any easier way than the manual routing? Thanks 107919 Regards, YY
Hi everybody: I am using AMS H35 tech for HV-Processor M0 Chip. The P&R and drc have passed. Now I am using Assura to do LVS and encounter some wired problems. Who has some ideals? thanks and regards error: Device 'cds_thru(Generic)' on schematic is unbound to any layout device Device 'RDIFFP3(RES)' on Layout is unbound to any Schematic de
Hi, I am using AD Summer 2009 For PCB Designing. Can any one tell how to locate (Highlight) exact location of unwanted short circuit in PCB after running drc.
you could read the drc report from Assura in Encounter and fix them by hand. but first, the design from Encounter is drc clean? if yes, you must understand why these error are not seen by encounter.
105140 I am trying to verify above drc error (Enclosure rule). This is what is there in the assura rule file. L48775=geomStraddle(Nwell Nburied) L92003=geomAndNot(L48775 Nburied) errorLayer(L92003 "NBL.E.1: Minimum Nburied to Nwell enclosure >= 0.2 um") L91383=drc(Nburied Nwell enc<0.2) (...)
HI I AM FACING A PROBLEM IN drc CHECK IN SCHEMATICS Checking Electrical Rules error: Port has a type which is inconsistent with other ports on the net CAN ANYONE TELL ME HOW TO SOLVE THIS THANKS IN ADVANCE DEEPAK
I am new to MG calibre tool. I was trying to do a drc for simple NAND standard cell. In calibre RVE it throws error check GC.C.1 GC.C.1: GC Coverage less than 0.14 ( GC.C.1 ). I was hoping that i should get a clean run for std cell in a library. what is this GC coverage error? thanks
PO.R.4 { @ PO intersecting OD must form 2 or more diffusions except LOGO and RTMOM region what is this drc error ,I couldn't figure it out.
I would like to make a package symbol for a printed coil in Allegro 16.6. This coil has two pins that are obviously shorted together through the printed coil. Because of this short circuit, I get a drc error. How can I solve this issue and define a printed coil as a two pins component?
What is an NSD layer in CMOS devices? Why is is it used? When I run a drc, I am getting the following violation. NSD Space NSD < 0.350 . What does this mean?
I am working on the layout of instrumentation amplifier, my design is hierarchical i.e. there is three op amps in it. The layout of op amp is drc and lvs clean but when i instantiate the layout of op amp in the layout of instrumentation amplifier i got the lvs error. LVS error INCORRECT NETS
Hi, What is the difference between using dum and dg in LSW? I have an error in drc when I don't use dummy(all Metals and poly and active) in my design. But I need more information about this error and the reason of that. Thank you
Hi need input for this drc error. I have a powerfet that gets this flag. Can someone explain what this means?
There is an error in Calibre drc It says that I should not have any device in the corner of area... Then I think I should use a layer to define the area of layout. But I don't know which layer I can/should use? Thank you
Hi everyone, I can pass the drc and LVS. But when I run PEX, an error occurs: error MAC3 on line 2498 of $TECHDIR/LVS/Include/.lvs_extract.cal - duplicate DMACRO definition name: SUBC_PROPERTIES. Can anyone tell me what I should do? Thank in advanced
Hi, guy, I ran drc checking with cadence virtuoso diva. Usually the checking method is "flat". I chose "hierarchical" as checking method this time but got all error markers as shown in attached figure. If the checking method is "flat", I can remove all the markers in menu: Verify-->Markers-->Delete all. But this time I cannot
Hi, I am designing a capacitor with low parasitics. I tried to layout with (Poly1 conntected to M1) with (Poly2 conntected to M2). After I layout Nwell+Poly1+poly2, there was no drc, but after I add metal 1 on it, it has a drc error "Poly2 to unrelated metal1 spacing is 0.6um". I am designing in AMI 05um process. Thanks
What is the difference between an ERC error and a soft check error ? Why in LVS we have these two as different checks? ERC is an independent check program, can be run on schematic already, i.e. long before layout, drc & LVS, hence usually is not included in the LVS set. It is a program which che
Hi! I have a problem with Calibre Interactive. When I try to run drc for my layout verification ,it gives the error ' The following products could not be licensed sufficiently". Hope somebody can help me please..