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357 Threads found on Drc Error
I want to make a pcb board other than rectangular shape, like polygon shaped. How can i achieve this in Proteus ARES, without any drc error.
I am trying to load drc error report generated by a svrf script in encounter. But when I try to load that in Encounter i get the following error. loadViolationReport -type Calibre -filename Parsing the Calibre violation report... **error: (ENCVB-11): Invalid scale value. Please help !
Hello all. I finished my layout for an inverter a couple of hours ago and ran drc and LVS with no errors (they were successful). I then needed to make a layout for an xor gate which used two inverters. After I used the "pick from schematic" option, I instantly ran a drc check, which then gave 228 "Edge not on grid" errors. (...)
I'm a new Eagle user and I created an SOIC part with a small heat pad in the middle. The pad is on the bottom and at the top copper layers. The bottom pad is purely for soldering convenience sake. Its easy to solder the pad by heating the bottom pad with your soldering iron. Now, the board has 2 layers and the bottom one is all GND. I've attached a
I'm using calibre 2011 with cadence IC6.1.5 (Centos 6.3 OS) when I start calibre drc, I get the following error RVE server socket has not been initialized the license server starts normally without errors plz, help me
do you have any reference document for these kind of common errors? Not really. Read the drc doc. Then read the drc rules and try to understand them.
Hello, I keep getting the above error when attempting to run Assura drc on a simple layout of an inverter. I am using IBM 90nm technology. Additionally, here are some of the errors in the Cadence terminal: *No tech lib map file 'assura_tech.lib' or 'pvtech.lib' found. *No rule sets can be created because there are no defined Assura (...)
Hello, I Keep getting the "Failed to build VDB. Cannot submit drc run" error when I am trying to run Assura drc in my layout. In the cadence log, it shows that many layers are undefined as well. We are pretty sure it's because we are using Assura version -614 and layout version -615. Is there anyway to get around this problem? Thanks.
Hi, I am getting the following error on running drc ! GR268b: RX(N+ Jct) to Substrate Contact space <=53 um First I made the schematic using an NFET from bicmos7hp library of L=180n and width=600n and then I used Layout XL from Design synthesis. When the Layout editing window opened, I did "Gen From Source" and still I am getting the above
I am designing a simple op-amp color organ in diptrace. but dont know why there are errors showing in drc. please let me know where to rectify . I'm attaching some screenshots. Thanks 94977 94978 94979
The filler cell are required to have a continuous n-well between each std cell, and certainly fix this latch-up drc.
hi tamil, first do one think tools-->database check select all and then run or else do update drc now generate artwork if you get same problem start-->cadence-->product-->select pcb editor utilities in that select DB doctor select current board file as input file and select output file as same file and then click check .after that check viewlog (er
I meet one ViVADO error, error: Rule violation (Pdrc-133) SLICE_PairEqSame_B6B5_error- Incompatible programming for SLICE_X283Y355. B6LUT and B5LUT must have a compatible equation,lower bits must be programmed the same. It is so strange for me? Anyone find the solution about it?:?:
the job 'hercules_drc_25' started on host 'localhost' with processid 8498 fialed to start or complete successfully ; the job return code is 34 i'm designing an INVERTER layout and when i run drc an error like that occur. plz help me!
1. error-free drc run and GDSII tape-out of your own data base, totally based on the fab's/foundry's PDK 2. Your own test pattern generated considering the fab's/foundry's specification re. format and error coverage. For more info see the fab's/foundry's detailed docu, which always is confidential.
I'm doing layout using TSMC 65nm. I'm designing current mirror. And to increase accuracy, I wanna add two dummy gate in mirror's edge. When i run drc, it cause "floating gate" error......OTL... What should i do?
Hello All, In my design i am using differential pair and i have set all the rules required for the differential pair routing like clearance, matched net lengths, differential pair routing and differential width. Everything is working fine but matched net length rule is not logging any Online drc errors, every time i have to run drc (...)
Hi all; I am working with AMS H18, it is same with IBM HV 7SF. In the floating gates drc (Antenna Rule) check, I get the following error message: "Gates over RXHV touching MT touching FT/FTBAR must be tied down by MT metal." First what is the meaning of tie down? Second how can I achieve to tie down gates by MT metal? Third, when I us
i am not able to view the drc errorS. Once drc is run, the error window is not opening. It is actually running,error window alone does nt open up.Once it has been run , it is not possible to run it afterwrads.. , they will show the window that drc running is in progress, do you want to stop (...)
any one face new type of drc error and rules in 45nm technology... help me ....