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357 Threads found on edaboard.com: Drc Error
Hi everyone, I am using Cadence PCB Editor 16.3 to develop a board (4 layers). I have 3 vias connected to the GND_RF net. The Top Layer and Inner2 Layer have a plane connected to GND_RF. The Inner 3 Layer has a solid fill shape connected to the VCC Nets (VCC1 and VCC2). The bottom has same nets connected to the GND_RF net. The problem produce
I am sorry to ask you a side question, is it possible to do the layout in the Orcad ? while doing drc in schematic , I am getting error like error(ORCAD-36055):Illegal character in \etu-v01r10(1)\.
I have installed cadence IC6.1.5 and Calibre 2011 (centos 6.3 OS) when I run calibre drc, I get the following error error: Invalid Calibre software tree: /Tools/mentor/calibre_11/x86_cal_2011.2_34.26 and calibre doesn't start plz, help me
hi all! i have designed a whole layout in orcad layout plus. but in the end when i try to make gerber file it gives the option that gerber viewer can't open the gerber file. it is giving the following errors as shown in the picture below. 85414 here it is showing many errors in each connection. i checked it no con
Dear all, I have still problem with mentor icflow 2008.2o and IC station 2008.2o. when I run drc (ic rule) i get error message: // error: $raise_status returned error status at line 90 of file /usr/local/mgc/2008.2o_rhelx86linux/icflow_home/shared/pkgs/ic/userware/En_na/drccmd.ample within (...)
The default drc rule can give errors when you try to use SMD components which have a low pad to pad clearance. Edit the drc rule to math your design
Have an interesting Cadence error, after running drc, "Has Multiple Stamped Connections". I know what it is, something to do parasitic resistance calculations on more than one substrate connection. Any idea where I can find the info to fix the problem, already tried Cadence help and Google. Have you seen this error? This circuit is an (...)
Dear all I am using NMOS transistors. when I do the drc I got a message of "floating NSUNB" while as I think i should not receive like this message if the nmos has PSUB ?? thank you
i have encounter this 2 error when running the drc check anyone know how to solve this 2 error please help me? nwell overlap n active tie down >= 0.20 PP/NP overlaps OD => 0.25
Hello All, I designing a circuit in Bicmos HBT Process.I am using NPN. I have used the Pcell of NPN but it does not have the substrate.And when I do a drc , I get error "Bad Substr......" I will be thankful if anybody can throw some clue to solve this SB
i encounter this error PP/NP overlaps OD >= 0.25 and N-well PICK-UP to PMOS max space < 20um i am only doing a inverter layout hope you help me. i am new to this software ( virtuoso 5.1.4.1) Hi, Just put my thoughts on those drc 1.PP/NP overlaps OD >= 0.25 -- I think this NP/PP Spacing to NP/PP without int
Hi all, I am a fairly new user using calibre tool for drc error check. I have not finalized my design and want to perform drc check on the blocks. Suppose an inverter.. I saw from earlier threads that there is a way to avoid chip edge related error by choosing the cell switch on. Can someone please elaborate on this? (...)
When I start drc I get an error that reads: couldn't read file "tabnotebook.tcl": no such file or directory I was running calibre yesterday and today it doesn't work anyone have this error?
Are your drc rules set differently in CAM350 to how the genesis ones are?
hii , I am new to layout . I use assure for drc checks , and I have an error : "PP.EN.2 3 enclosure of PW strap >=0.03 " I only used OD (oxide diffusion ) on the layout editor , and th error came by . Plz help me in resolving this , thnx
Hi all, I am new to calibre interactive nmdrc 2010.2_25.18 tool. When I am loading rule file in drc form then tool shows below error. error while compiling rules file ./ts18pm/calibre/t.00_00_01_scr/drc_TS18SLPM_CALIBRE: error RES2 on line 124 of (...)
Colleagues, I?d like to make a board where some of the vias are on SMT pads. I?m aware of the potential assembly problems, which via-in-pad might cause. My circuit will be hand assembled. When I try to make via-in-pad, Eagle generates a pop-up message ?can?t set via to layer 1?, or draws a big yellow X on the layout. Is it possible to suppre
Hi, I have two questions: 1. Why for some cells, IBM_PDK and Calibre is not shows on Virtuoso menubar? 2 Why I get "RROR: Specified primary cell XXX is not located within the input layout database" error message while doing drc on some cells? Where is the "input layout database" and how can I add other cells to this database? Regards
Hi all, I import a GDSII file in IBM 7RF technology and while streaming in I specified the LayerMap file (cmrf7sf.layermap) but while I try to do Calibre drc it shows me the following error message: ibmPdkrunCalibre("drc") Starting drc on top cell in window:3... Unable to find valid layer mapping table. Please enter (...)
Hello, I am now doing the post simulation of a ring oscillator and my drc and LVS are ok. But when it comes to PEX the problem is that, the parasitic r and c have been in the pex.netlist but their symbol cannot be seen in the calibreview generated , in which they should be res and cap symbols in analogLib according to calview.cellmap. I c