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357 Threads found on edaboard.com: Drc Error
I am using IBM .18u technology and keep getting this drc error related to my nwells and have no clue how to fix it. drc error message: (((NW not cover by GRLOGIC) or (NW touching BB)) touching ((PC over RX)) not over DN must be tied down by the time M1 is complete. valid tie down 1 : pdiff in NW is connected to ndiff (...)
Hi, I already installed the IBM 90n 9LP design kit from MOSIS and designed an inverter layout to test drc and LVS checking before starting use this DK. During LVS running the following error ocurred: error (AVVSI-10001): Input layout is incomplete. If you still want to continue the run, remove undefined placements from the layout or (...)
Hi all, I am getting an error in my layout while running the drc . The error is PSUB_StamperrorFloat I dont have any NMOS devices in my circuit layout. revert me back at the earliest. \
1. We have Configured the 65NM UMC library successfully and able to run schematic level simulation in spectre. 2. I have converted the schematic into the layout . During this time MOS Transistors are displayed with a cross-mark(see the attachement). 3. Then when i try for drc run, drc VDB error message is occuring ....
Hello My circuit is a decoder. I have created the layout of the circuit. I am using assura ams H35. And i have already passed successfully from drc and LVS runs. The next step is to perform the parasitics' extraction and run post layout simulations. But when i perform the parasitic's extraction, I get this error error (LBMI
Hi, I have IC614 installed. drc and LVS are running fine but there is a problem facing during QRC run. Before the details of the error, please have a look at the configuration of my current setup: Platform: Cent OS 5.8 Installed Cadence Products: IUS08.20.017, IC06.14.512, MMSIM10.11.218, ASSURA4.12-614 Technology: UMC_180_ANALOG [
hi all, I am a newbie to cadence.. when i was designing layout for xor gate...i found the follwing drc errors 1.Nwell-stamp error float 2.p+SD to nwell distance<=10um kindly help me out of these errors thank you
Hi I have layout of complex function out = (AB+C)D . The drc show no error but LVS show : Terminal "G" on device /+7 should be connected to /Cb instead of /Db (deivce +7 is pmos). I cannot figure out the error and need some help. Please help me with this. Thanks a lot.
Actually an ERC error message (probably run simultaneously with drc). If you intended that VOB1 and VOB2 should be separate nets, the warning tells you that these nets are actually short-cut with VDD. So you should not ignore the warning. If you, however, have labeled the same node with 3 different labels, the warning just tells you that VD
... involves logical functions between layers AFAIR saveDerived saves its created polygons into a drc error (or drc warning) layer. You could then make all layers -- apart from this layer -- non-selectable, then select all and copy them to a different cellview.
i m working on cadence.. when i tried running drc. i got psub stamp error float. what s this error.. pls help
dear all, i have implemented an inverter in synopsys custom designer. and now i am trying to do drc, LVS and Parasitic extraction. Problem is when i do the drc check then i could pass it. but when i try to go for LVS, i get errors. can any body tell me whats wrong with my procedure. i am attaching the relevant files. I using (...)
Hi all, I want to perform post layout simulation of sram cell in cadence 6.1.4. I have completed drc n lvs steps successfully with assura.But i can't extract gives error that "no directory found". I have attached screenshots of settings for directory please help me if anybody can solve this problem...Thanks in advance...[A
Hi friends, I have a doubt in Mentor Graphics (Pads)... While performing drc it does not shows error for same net. (Gnd & Pwr) i.e. either gnd same net or pwr same net the error is ignored... How to run drc for such condition? thx... -Goku-
Hi friends... I am working in pads 2009... I have encountered a problem while performing drc... The same net errors are ignored when we run drc, (Gnd & Pwr)... How to solve this problem?
After LVS process , i am getting few errors. drc was without any error. After running LVS , got 6 errors ... Layout is of inverter with A as inputs ,Y as output , alongwith Vdd n gnd. 1) Missing ports 2) property errors. In Missing ports , i m getting error in every port i.e. in (...)
Hello, Iam trying to design and simulate cmos Op-amp. I have done drc,LVS and QRC without any error here is a screenshot: drc: Note: there are some warnings however my professor asked us to ignore these errors. LVS: Image - TinyPic - Free Image Hosting, Pho
I have used Eagle occasionally. There was definitely a drc available. I don't expect that it has been omitted with newer versions.
If it is a drc marker then check you Preference settings for drc marker size but it seems or to be a track which is giving drc error because it is shorting pins of connector to Mounting hole. There is no option like mechanical pins in Altium you cab define as other pins aand give them any Pin name as to differentiate it (...)
Hi, I have several sram macros in my design generated from memory compiler which cannot generate GDSII file. I streamin the design in Virtuoso and tried to run drc but have this error: error: Cell sram_1kb is referenced but not defined. When I streamin in Virtuoso, there are warnings related to this macros: WARNING (X