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357 Threads found on edaboard.com: Drc Error
It's difficult to navigate in errors in Altium. I'm running drc and it shows me a report. I'm clicking on an error it goes there but it's not zooming enough and the markers are very small or unnoticable. So you try to find the error using coordinates. This is a painful process. Is there a better and easy way?
Hi all, I had problem when running Calibre LVS for my design. It couldn't recognize the rpoly2 I used in the design. The simulation and drc check were ok. Anyone has experience about this point? Please help me. Thanks. error: No matching ".SUBCKT" statement for "RPOLY2" at line... error: No matching ".SUBCKT" statement for "RPOLY2" at (...)
Hi everyone, I am using AMS 0.35um process.I am getting BAD_SUBSTR_SUBTAP_FLOAT_ERC error while running ASSURA.Please someone help me in debugging this error and how to solve this. Thanks
Dear All, When I run drc and LVS for my design, there is an error: error while compiling rules file /home/user/amsc35/calibre/c35b4/c35b4c3.rules: error POLYNET1 on line 1738 of $AMS_DIR/calibre/c35b4/cac35b4rules_all.run - the POLYNET operation is obsolete. Please use CONNECT or other alternative or contact Mentor (...)
Use the search facility here in the forum,you will find various reports for this problem from the past and maybe some solution. Also : 1.)Make sure that you have the correct metal stack attached to your library. 2.)You have the correct paths in you shell file (.cshrc file for example) for the Assura tool and that you use the correct version for y
I am using tsmc90nm. I use autofilling tool provided by tsmc to do filling. When I didn't merge the dummy metal created by that tool, my lvs was correct. But when I merged it, mimcaps and several pins were not correctly bonded. Any idea why? ( My lvs with the merged dummy metal used to be correct). And my drc is clearn.
Hello All, I have designed a 27 GHz LNA in 0.18 TSMC rf technology. I have 6 rf mim capacitance as dc blocks or bypass ones. when i run my LVS, a drc error appears like this "ntap connected to Ground" for rf mim cap and when i connect their body to VDD metal, error becomes " ptap connected to power ". Can anybody help me please? i really (...)
Hey guys, I suffered some problem while mapping in Xilinx ISE 9.1. And I find there are several similar posts about this problem in Edaboard ,but not any answer.I found some resolutions in Xilinx's website, like "10.1 Floorplanner - "error:Pack:679 - Unable to obey design constraints." (No drc check on Virtex FF clock)" [url=www.xilinx.
You should first check the options of your drc deck. In TSMC data there is usually a variable to define the check area: //#DEFINE ChipWindowUsed // Turn on to specify chip boundary directly by following variables VARIABLE xLB 0.0 // x-coordinate of left-bottom corner for user defined chip window VARIABLE yLB 0.0 // y-coordinat
hi freds!. i am using Eagle software to create a PCB design. I have lot of Stop mask error in drc Check icon.How do resolve the problem.herewith i enclosed one of the image. this problem only occur when using TSTOP Layer. waiting for your Valuable reply. images.elektr
Hi, Your prb is an ERC and not a drc probkem.
Every PDK has a "grid" (lowest step you can place or move an object to). You have information. You have your foundry PDK docs and you have your drc deck. You could read the code and determine what the grid is. Don't play helpless. Learn to dig. These errors often come from a chop or merge gone bad, creating a new vertex at a point you could no
I completed a ORCAD 10.5 schematic. I ran the drc with all switches set except check for SDT compatibility and had no errors. I attempted to run a Layout netlist (.mnl). It aborts very quickly and returns these errors in the Session Log: error Layout DB error code 18890, '1'. error (...)
Hi, guys, I have an error when I try to run the Chameleon tool in cadence for the layout drc Check. it looks like this: *** error: FlexLM was unable to grant authorization to use the 'Chameleon_Basic' feature. Possible reasons are : - all available 'Chameleon_Basic' licenses are being used - the wrong license file or license (...)
hi, As such there is no need to pass whole drc rules. as you are saying about the empty area of the chip .. so can you check the GDS layer no in that. another thing .. what's the format of Design database?
As I know there is no relation between CTMDMY layar and Density error of drc!!! CTMDMY (capacitor top metal dummy layar) is a dummy layer to specify your capacitor area, which is useful in LVS process. The density drc error is an error which is occure when the density of a metal is less than a percent (...)
...I can't see if there is any error in my design by looking at the .sol and .cmp there any other way? Most PCB design CAD softwares have drc tools wich allow to detect manufacuring rules violations. Had you performed that verification ? +++
There are no drc errors with what you have attached, but there are holes there. Maybe you could show a file with the errors? Keith.
u can create a layer equal to your chiplayout (genarally in 108 for TSMC 40g node) which is a prBoundary layer, this will give CHIPEDGE for drc run
you should include "EXCLUDE CELL " into the drc rules.