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357 Threads found on edaboard.com: Drc Error
i have got an error called "hr" while doing drc checking in synopsys. can anyone tell me what does that error mean?
can you plz explaiin me where I have to change. should I change in drc > Clearance then Wire or PAD or Via... Plz explain me Thanks
I am getting below error in Hercules drc run. Can anybody explain about this error and also how to solve this? PO.RL.1: ALLPOLY maximum length = 200000nm (after poly_sub cut) ... 2 violations found error DETAILS #####--- ERR_SELECT ----------------------------------- SELECT_CONTAINS (...)
I am getting below error in Hercules drc run. Can anybody explain about this error and also how to solve this? PO.RL.1: ALLPOLY maximum length = 200000nm (after poly_sub cut) ... 2 violations found error DETAILS #####--- ERR_SELECT ----------------------------------- (...)
Hi, all, When I'm trying to do drc/LVS/PEX verification with Calibre, it stops at the "Waiting for Layout viewer to export cell ...", while the CIW window shows "Calibre normal exit" with no verification results pops up. so what could be the reason? Thanks in advance.
I am using Cadence for the designing an flipped voltage follower. I'm a bit stuck understanding what these error messages mean in the drc checker. if there is a link where I can find an explanation please let me know, otherwise I'd really appreciate some help understanding the following: 1. Welnotr_StamperrorFloat (NWEL
hi, Can anyone tell me how to resolve the drc Skewedge error from the post layout simulation of VCO. Does it causes any problem in simulation.
hi all, i am working on floating point multiplication design on virtex5 FPGA board.when i run my vhdl code on xilinx ISE tool the following error is coming..... error:PhysDesignRules:1535 - Invalid connectivity used for DSP48E block e3/Maddsub_product_f_mult0000. When A_INPUT and B_INPUT attributes are both set to CASCADE, the input
Hi Guys, I have completed all the steps in the flow using Cadence tools till drc/LVS for an IC and am seeing some LVS opens to VDD. I think this may be due to lesser power straps. My idea of solving this problem is as follows: 1. Open the floorplan in Encounter. 2. Delete all the VDD power straps. 3. Add some extra power straps. 4. Save t
Hi, I've designed a digital chip with Astro, and there's no CEL view in the Milkyway Lib, when I check drc with calibre, it will cause many error because there no standard cell view in the gds file, so, how can I check drc with calibre now? thanks!!!
Hi! i use Cadence and Assura for the drc and LVS in Layout XL. I fill the form of assura LVS and choose the right technology files in each box and i choose the DFII option. BUT when i click ok an error message appears which says: "The specified SKILL device information file was not found". The technology files are correct and the assura_tech
Hi, Can anyone use the component rule settings in PADS router? If I set the component rule for through hole components it won't recognize for inner layers.For example in drc verification it shows the error only for component layer either it is top or bottom but not shows the error for inner layers since it is through hole (...)
Hi, all, could you help me? Assuraoa3.1.7, ic6.1.3, MMISM07 were used. when assura drc run for the firstly several times, they were successful. But afterwards it always said failed, and in the log file it wrote "error unknown: unable to create library "AssuraOutLib"". What's wrong with Assura drc? Thank you in advance!
Hi I have passed drc and LVS. I'm currently running Calibre PEX to extract my layout. However, when I extract using this setting (L+M, self+mutual inductance), this error shows up: error:Net information could not be built. error:The inputs for the inductance engine were not properly built Can anybody help me. Thanks
Hi I have passed drc and LVS. I'm currently running Calibre PEX to extract my layout. However, when I extract using this setting (L+M, self+mutual inductance), this error shows up: error:Net information could not be built. error:The inputs for the inductance engine were not properly built Ca
Could anyone help me how to turn off the flashing after running the drc? In the Layers Window (LSW) search for a layer named something like drc error and set it to Non Visible (middle button, AFAIR), then click Apply and/or do a redisplay (^R).
Hello there, My P&R script works fine when I run it for the first time after starting Cadence Encounter 8.1. If I run it more than once, I get OffMGrid drc errors. Thus, I need to restart Encounter every time I want to run the script. I have the 'freeDesign' command in the beginning of the script, so Encounter should clear all information about
once delet the net and reconnect check the drc and then also its comming means..some ware u are no given the net name clearly....
Hello Firstly i am using OrCAD 15.7 and designing the board using PCBEditor. I have designed a board wherein i am getting a drc error for the distance between two parts. This is because i have placed these parts very close to eachother but on final board i am sure that it will not be a problem. Now how can i rectify this. I know there
Hi serhannn, Please when posting a drc/LVS/QRC error you should be more specific,that is you should show the exact error given by assura/calibre etc...For your case,i think that you should create a n-well contact ring around your pmos transistors and then connect this ring to Vdd.Give it a try and see if this corrects the (...)