Search Engine www.edaboard.com

Drc Error For Layout

Add Question

58 Threads found on edaboard.com: Drc Error For Layout
Hi iam using layout plus and new to FPGA based board design, my error is iam getting No Connection to plane-when i do drc for SMD fanout. how to solve this error. I created split planes for all Vccint,Vccaux and VCC0 this iam getting even for ground,help me please....
how can we solve that drc error. i didn't understand the density of metal. how can we improve density of matal. pls clarify my doubt.
Hello, all i uses a layout of a spiral from ams hit kit 0.35um technology which is designed and enclosed in the kit, The problem is: i uses diva for layout, when i do drc Check, the following statementis an error message: spiral_term contact does not connect to two layers any help please??? (...)
Hello, all i uses a layout of a spiral from ams hit kit 0.35um technology which is designed and enclosed in the kit, The problem is: i uses diva for layout, when i do drc Check, the following statementis an error message: spiral_term contact does not connect to two layers any help please??? thanx (...)
for my layout, I have passed the drc and LVS checking using Assura. As I do the extraction in RC or R only extraction mode, it gives out the error and stated: *error* FAILED ASSERTION at ?reconnect?: RCX net 1722 cannot be mapped to LVS net If I use C only extraction mode, it could do the (...)
for LVS- there might be missing instance or missing layout. Your netlist and layout are not match. There might be some elements that you forgot to put on your layout. for drc- look on what device type it should have been and check the drawing rule if you have put all the (...)
I do use the calibre for the layout verification. But it becomes difficult to rectify the drc errors looking at the drc.db (error database having x-y co-ordintes). Does anyone have any sort of interactive (GUI) for drc debugging for the (...)
I do use the calibre for the layout verification. But it becomes difficult to rectify the drc errors looking at the drc.db (error database having x-y co-ordintes). Does anyone have any sort of interactive (GUI) for drc debugging for the (...)
ORCAD layout errors after autorouting, Although NO drc errors were flagged: (Lay-Err1) This error was under silkscreen print and therefore not visible: (Lay-Err1b) This error shorted the the output of an fine pitch IC to VCC and destroyed it. There were other (...)
Hi, guys, I have an error when I try to run the Chameleon tool in cadence for the layout drc Check. it looks like this: *** error: FlexLM was unable to grant authorization to use the 'Chameleon_Basic' feature. Possible reasons are : - all available (...)
Hi all, During drc, there is this message. error message: min density of Poly2 area 30% What does it mean? Do I need to put more Poly2 in my layout. Please advice. -no_mad
Dear all, I am using cadence 5.0.33 and drc runs fine without any errors (but there are some warnings like "layer purpose fair does not exist in the tech file"). When I try to extract the layout I get the following error. Extraction started at Wed Oct 18 14:57:13 2006 Assuring hierarchy instantiation (...)
I am layout a POLY resistor in the tsmc 0.18 um proc. The drc gives me no error, but when I extracted, this error "no stamped connections" persists. I googled for it, without much info. But I just know that it is caused by the lackk of connectino with the substrate. But there are only two terminals of metal (...)
Dear all, I have a question. I use tsmc 0.18 um and I run drc and lvs. I have two blocks ( ananlog and digital ). I don't have any resistors and capacitors. I run drc and lvs for two blocks and they are ok. But the analog part comebines with the digital part. It's a error for lvs. I use Calibre (...)
Hy guys Which of these ERC ( error rule checkers ) do you prefere for drc extraction of a layout. Anybody has experience with NANOSIM drc checker ( personaaly I've only experience with DRACULA drc). ? I mean for example if some of you have experience in checking a (...)
Hi Guys Has anyone used mentore calibre tool. I need some help for it. I am using calibre drc, LVS, RVE. Does RVE show any marker on the layout window when we click on the error or it just zooms the area. If any one has any information related to it pls let me know. Thanks & Regards. Tama
Just installed a new PDK for Cadence. When I do drc for layout, it keeps showing error like # INFO I/O PADS = WIREBOND# Could anyone give me some suggestion on how to fix this problem? I'm not a CAD guy:(
The best LPE tools is xcalibre or drcula .