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Sometimes I'd like to know what's the recent started threads in a forum. But top threads are most latest replied ones. I searched options in profile. It looks there is no setting to change it this way.
Hi , I am working on one project in which it require earth leakage detection >30mA on both positive and negative side. So,could you please suggest me proper reference books or articles and methods to implement it, because I am unaware of it. Thank you
hii, why requred to simulate atpg pattern in vcs but Synopsys Tetramax tool also option of run_simulation? Thanks,
I just got some great help on this forum to resolve a logic gate issue, so I thought I would try my luck with what I hope is my last issue. Below may be too much context and you may ant to skip to my "question" at the end. for background, the context is a battery management system for a 200 Ah LiFePO4 marine battery bank. The system (...)
we insert Mbist before scan insertion what effect ? Mbist insert after scan insert what effect Or problem occure ? Thanks
Hi all, I have a problem in defining RESETs in Spyglass DFT flow. Can any body point to me the correct way of defining the Resets in the flow. Thanks
As a beginner to VSLI design, I am using and learning Innovus these days and have two questions. Hope someone could help me. 1) set_db. The user manual has some sample flows with codes. It usually contains 'set_db' commands to set values for some attributes (the manual calls it database object.) These object usually is the attributes belong to
Hi All, I'm new to analog design. I need to design an 12V DC minimum 1 amp power source that takes input from 220V AC without using any ic component. I'm familiar with the transforming and rectifying. My only problem is I don't know how to design a steady voltage regulator. I'v looked up online but all of the designs uses ic components. Any resear
So I want to see what are the input patterns of the design which has an output of stuck at 1 at the output named 'outtt' of my behavioral verilog code (of course which I later synthesized)...what should be the appropriate commands for tetramax for this? :?:
Good day everyone! I need your help on this one. I'd like to derive the equation for the closed-loop input impedance of the circuit attached. The final form of the equation is also shown below. 157314 157313 Here's what I have tried 157316 I was stuck. Can you tell w
I have a Xubuntu guest on a Windows 10 host and I need to establish a serial communication between my notebook and the microcontrolled external system via serial connection. The notebook side is an USB port and the system side is a true serial DB-9 connector. The whole system works in the following way: i) I download a bitstream file from the
Dear All, I am trying to generate test patterns for a test bench circuit "wb_conmax" by opencores. I have successfully generated the gate-level netlist. And I had successfully inserted the scan chain. However, I am unable to generate test patterns. It gives following error 157326 The script I am using to generate is as fo
I'm designing a daughter board using OrCad layout (old, I know). The board has 2 40 pin connectors at opposite ends. Both connectors have VCC net connections to the main board. The main board has the power supply and supplies VCC to multiple pins on each connector. I routed the board to use the closest VCC pin on a connector. The issue I am havi
I have a PCB design with an onboard uC (ESP32-WROOM-32D) and voltage regulator (AMS1117-3.3). The PCB doesn't have USB comms or power, so I want to have a separate "bootstrapping" board which has those things and connects to the uC via a 4-pin header. Should I add a diode to protect the voltage regulator on the board with the uC when power is com
Hello, I am interested in learning about analog integrated circuit filters - Active RC, GM-C, OTA-C, Switched Capacitor Filters. Can anyone recommend books for learning in this field, with numerous examples ? I like the Valkenberg Analog Filter books and also the Laker and Sansen book. Any other books ? Any course notes or course websi
Hello, I'm new to the forum but hopefully you guys will give me some great advice. I have been programming microcontrollers for the past five years, only as a hobby but I do plan to move to this as my career, I am currently a machinist but I don't quite have the means for university yet. I'm 27, so should still be capable of learning (...)
Hi, for the error "incorrect ports" in Calibre LVS hierarchical run, why do some ports appear at the top level and others at the IP level ? What is the basis for them to appear at two levels like this ? Thanks, Aditya
Hello everyone. Currently, Im designing a processing element. This design is synthesis in Xilinx ISE Design Suite 14.7 using Virtex 6 XC6VLX75T-2FF484. I have problem on the timing analysis. The is no setup time and hold time reported as shown below. 157310 There is no slack for setup time and hold time. Durin
Can anybody please suggest me any resource on wireless power transfer coil design?
Hello, I'm new to the forum but hopefully you guys will give me some great advice. I have been programming microcontrollers for the past five years, only as a hobby but I do plan to move to this as my career, I am currently a machinist but I don't quite have the means for university yet. I'm 27, so should still be capable of learning (...)