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357 Threads found on edaboard.com: Drc Error
Hi, I would like to know if fixing drc and LVS impacts timing in any way. Is there a chance that it might degrade setup/hold timing?How exactly they are related?
Hi, I'm using the saed 90nm PDK with Synopsys Custom Designer tool. When I try to run the drc using the Layout Editor I get the following error: 136106 Also, I've got confuse to what type of simulator (Caliber or Hercules or IC_valudator) to use for drc. Please help if anyone knows how to solve it. Thanks!
HI I have a problem with virtuoso and AMS 0.35 I insert a pmos but I always receive the same error and I do not know how to fix it I puts a pmos for the library 136066 De assura drc indicates BAD_SUBSTR_SUBTAP_FLOAT_ERC but I think the substrate is well fed to VDD thanks.
Everyone, I'm using the IBM cmrf8sf 130nm PDK. I've recently come upon an error I have not encountered previously and am unsure how to clear it. From what I can tell, it stems from the NWell connection for my PMOS devices. The Calibre drc error reads: Check GR134: Floating (NW not over T3) found! - NWell must be tied down by M1. (...)
minimum top via enclosed by metal top 1 is 0.01micron... How to fix this error.. I am using 8Metal layer process? It appears when i place metal 6 and Top metal via top.
Hi there, I'm making an OTA layout in Cadence, ams 0.18um (cmhv7sf). The only drc error I have is about I/O wirebond - it says that some transistors don't have body contact while there are n-well contacts. When there where contacts on the left and right side errors where the same. 133931133932
Hi, Show us the board detail and the complete drc error, which layers are overlapping. Klaus
In Altium, I have a non-plated through hole with a pad. The pad is assigned to net GND. I have a polygon pour defined as GND. When I pour the polygon, the pad has thermal connections to the pour, as expected, but when I run the drc I get an "unrouted net" error associated with that pad. I wanted the pad, connected to GND, I GOT the pad conne
I am using ams 0.18u technology and keep this drc error GRHV10. My layout looks like 1. Nwell 2. P+ (BP+RX layer) arround Nwell 3. Inside of Nwell is a N+ (RX layer) plus a square contact (CA layer) No when i get following drc error message: GRHV10:(DIODENWX not over (DIODE or GRLOGIC) is not connected in parallel (...)
Hello, Placing an SMD component (SQFP48 or similar multipin squared component) in Ares, shows a lot of drc errors. If I check the Design Rule errors, the Specified Clearance value is 0th and the Actual Clearance Value is negative (-2.22, -3.13th....) Reseting the Default Values makes no more change. I am stucked to this point. Some (...)
I guess I'd begin with, is Assura the selected drc engine? If {whatever} doesn't like the drc deck that's purportedly for Assura, you have to wonder who you're talking to. And then I'd be looking to gpdk message boards for any stuff about drc setup particulars for the 45nm kit.
Can anyone help me with fixing drc/LVS violations. Does anybody know whether IC compiler can fix these errors itself or not? I tried to use signoff autofix drc option of IC compiler which is related to IC validator, but I received these errors: error: The ICV environment variable has not been specified. (...)
In Eagle PCB I try using vias to route the signal to bottom layer to avoid "trace overlap" on the top layer (as in the attached picture). But now for some reasons I get overlap error on the vias. I played with many clearance, distance, and size values in drc settings, but none of them help. Please let me know if you have any idea how to solve t
The error is self explanatory: The drc for pad-to-pad clearance is configured on tool as 20"th" but you drew them just 9.56"th" apart. You must move away the pads from each other.
hello everyone! i have designed the symbol view of cmos amplifier and now i am creating the layout of it. While checking the drc rules , error named "tap area" is being observed. Can anyone help me in resolving this error? regards SJK
Hi All, While executing Calibre top_cell m_rtcm run. Getting below error. Kindly assist me in resolving this ***************************************** ZOR ICC ENV *********************************************** * Starting Script : zor_runCal * User : mrksingh * Time : Fri May 13 20:23:21 2016 * Main Env
If you are referring to the error highlighted during routing process, there is an option to enable that feature, something called "Online drc"
Hi, We are experiencing a drc error on one gate of a test chip. The signal goes to a MOM cap and a pimplant resistor chain and no where else. This gate signal is now being flagged as a floating gate with the drc error as PO.R.8 { @ It is prohibited for Floating Gate if the effective source/drain is not connected (...)
Now that the information about the layers has ben established, there isn't enough space for me to add (without drc errors) an M1-Pdiff contact for the bulk within the green rectangle. Is there anything I can do?
I am running a simple drc check in Cadence error is PP.EN1:{NP OR PP} enclosure of PO (except of PO) >=0.15um. I am running a simple NAND circuit with one Pmos and one Nmos transistor.I use a via to connect the input(metal 1) with the gates(poly).