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Drc Spacing Error

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19 Threads found on Drc Spacing Error
I am using an STM32 microcontroller component in my design and getting lots of clearance errors. I am using default eagle drc file and haven't modified anything in the library. The library, schematic and brd file is attached. Thanks in advance. 125259
After fixing almost all the drc errors, I'm still getting some clearance errors in AD7490 component. Could you help me solve this? 116966
Hi, can someone explain me what is happening with PCB editor and this drc error, Line to SMD Pin spacing (pictures attached)? Explanation: First, I route the USB_P trace, and no drc error is shown. Then, I don't know how, the USB_P trace was hidden, but drc error (...)
NIMP width must be >= 0.4um NIMP to NIMP spacing must be >=0.4um how to correct these errors.pls help
Hi I make a tpr file that is for description of a one-bit full adder. I add it to L-edit with standard library(from SPR->place and route).the L-edit creates layouts for core and chip,but these layouts have some drc errors that are about select to select spacing! Also when I try to make a spice netlist, there is an other (...)
Hi, I am designing a capacitor with low parasitics. I tried to layout with (Poly1 conntected to M1) with (Poly2 conntected to M2). After I layout Nwell+Poly1+poly2, there was no drc, but after I add metal 1 on it, it has a drc error "Poly2 to unrelated metal1 spacing is 0.6um". I am designing in AMI 05um process. Thanks
do you have any reference document for these kind of common errors? Not really. Read the drc doc. Then read the drc rules and try to understand them.
i encounter this error PP/NP overlaps OD >= 0.25 and N-well PICK-UP to PMOS max space < 20um i am only doing a inverter layout hope you help me. i am new to this software ( virtuoso Hi, Just put my thoughts on those drc 1.PP/NP overlaps OD >= 0.25 -- I think this NP/PP spacing to NP/PP without int
Hi I have this drc error (vertice is drawn off-grid) what does this error mean?i have no information about it except the previous statement can anyone help me??? thanks in advance
hi can anyone tell how to fix drc violation after done with post routing? i got one M1 spacing to find the location of error in the layout? also i got lvs errors like missing port vss on net: vss how to clear lvs error too Thanks, chandra.
When you only have drc errors (but LVS clean) you can run post-layout simulations. Nonetheless, the results might be incorrect: let's say that the drc error you have is metal spacing, the capacitance between those 2 nets will be a little higher...
Hi I found there is one off grid error in the file i submitted yesterday. Can some one pls tell me what will happen to it? They said the project is released for run and ask me to resubmit it asap. I want to know what if i miss it, what will do with this off grid problem? This trace wont be able to manufacture? or they will send it back
why not split that big transistors into smaller ones then make the arrangement ABAB? Hi all. I have runt into a drc error : MAXIMUM n+ DIFFUSION TO NEAREST p+ PICKUP spacing(INSIDE P-WELL OR TWELL) IS 20um I know this is resolved by adding taps or a guard ring around the device. Problem is that I get this error for (...)
I'd suggest to find in the drc rules file the corresponding rule (which generates this error marker and message). This should give you a hint if possibly an inhibit layer (a layer which disables the drc check for special regions like pad ring) is missing. Actually this also should be described in the PDK docu.
hi all.. I am doing layout in cadence virtuoso tool. When i run ASSURA drc(Design rule checking) to debug the errors its showing one error like"MAXIMUM n+ DIFFUSION TO NEAREST p+ PICKUP spacing(INSIDE P-WELL OR TWELL) IS 20um. Its indicating at every NMOS in the design. I am unable to clear this one. plz help me out .
Hi vlsitechnology, Yes you are right... Find some more from my experiance. LVS: Open circuit short circuit Different no.of Ports Connectivity error Property error ...... etc drc: Latch-Up violation Min space error Metal Enclosure violation Fat metal spacing violation Poly Endcap (...)
I have a design which using Astro to do APR.... In the Physical Verification state, Astro check drc result is no violation. But check drc in calibre have violation. Can anyone tell me how to fix the drc violation?
hi, I am doing a asic semi-custom design. While doing a drc check in virtuoso, i put a exclude layer on the standard cell to avoid the tools to check the standard cell. This means im only checking the drc for interconnection between the standard cell. Eventually, i still have a errors after doing the drc check. The (...)
When I use Ap0lll0 to Design my Circuit , I meet These questions: Timing graph cleared. #(xdb_copy.c: 1078) Net VDD with no sink (1 times) #(xdb_misc.c: 644) xdb_fill_port_position() port 'div' no pin found (7 times) drc Brief error Summary error Type Num Description Met1 spacing 100 metal1 minimum (...)