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19 Threads found on Dsp And Pll
i guess in its code use fft code but with this micro and this freq sampling from lcd and this osilator how its posibble? The FFT function requires a lot of the uC resources and unless runing with a dsp compatible ALU, will not be able to get the result realtime.
what is your application? you need a pll that its output follows voltage angle and a Park transform. then determine Iq (which is perpendicular to voltage vector) amplitude according to your demanded power factor. all can be implemented by software in dsp or MCU. Good Luck
i want to make a software pll using dsp controller...i have googled a lot and found many links but mostly are in paper form i.e. they describe the conversion from analog to digital and the transfer functions of that... i am more of a controller guy so dont know how to implement them on controller...... if anyone has (...)
Sir, I am doing a project on dsp based fm receiver for my final year project. I want to demodulate the IF signal from the receiver and get the FM multiplex signal. I am using zero crossing as the demodulation method. always @ (posedge sclk) begin data_now<=adc_dat; if((((data_prv<8'd100 )&&(data_now>8'd100))||((data_now<8'd100)&&(dat
Is the fundamental frequency constant, within a reletively small range +/- 5% ?. If yes, use a pll to decode the signal for example a NE567 or 74HC4046A. If no, than you have to do much more work and the best way is use a dsp and perform a FFT is possible.
If you have access to something to measure the phase noise (like a good spectrum analyzer), the phase noise measurement tells you more. For instance, you can deduce the pll control loop parameters, and see stability issues in the phase noise data. I think people using digital methods (dsp, adc) tend to think in terms of jitter, while (...)
Regarding basic pll properties, there's no difference between a 60 Hz and a 60 MHz (or 60 GHz) pll. At 60 Hz, plls are often realized as dsp design with an "analog" mutiplier and a sine reference voltage, but the operation is basically easy, because you don't have to fear abrupt phase or (...)
You can use a one-phase pll to detect the phase of the input voltage or current. The control algorithm of the pll can be easily implemented in a dsp or even in a PIC.
Hi guys! I'm doing a project: using a dsp to demodulate a digital packet which is modulated by BPSK. Because the phase noise is a little big, so I decide to use coherent demodulation by a digital Costas pll. I've found a pretty good tutorial about costas pll named by google. (...)
I have got a altera stratix II dsp board and built a nios softcore cpu inside. I try to drive the fpga using a clock from a external hardware. My problem is the clock form external hardware cannot drive the pll inside the fpga. When I monitor the clock to be input to fpga, the duty cycle is varied but meaured frequency is still 66MHz. (...)
Hi, I'm using TMS320F2812 dsp. I want to operate this at variable speed on the fly. One way would be by generating different clock outputs at different instants and provide this as the clock input to the dsp. Another would be to change the pll settings. Is there any other mechanism? Also, would there be any side effects (...)
the new trend is to make All digital pll , or add some dsp functions to the pll to control the jetter and phase noise
I'm designing an frequency multiplying with digital implemetation. I intend to use the pll method. But I dont know how to do a digital pll using dsp ( in my case, I use dsp TI F2812 ). Could anybody help me some information to do this ? and another problem is, the output signal that I desire to get is no (...)
well in analog may be pll or high speed data converters on FPGA dsp
main the mix-signal system design. include the analog signal and digital signal, such as ADC/DAC, processor, dsp, IF etc.
Hello, I want to synchronize an internally generated (in dsp) sine wave with an external TTL signal. Doing it I want to generate a sine with the same frequency according to the TTL signal that is fed to my board. I used to measure the period of the external TTL signal (Timer) and generate the sine digitally in my dsp. While doing (...)
I need a volatile fpga with >50k gates (i not need internal pll, dsp functions, special i/o). Which is the best for cheap cost?? Regards
Hi all, I am designing a dsp board with Adsp-21161N. My idea was connecting 8ns SRAM to the external data port. The input clock should be 50MHz and the core frequency will be generated by pll with factor x2 -> 100MHz. Then I had a look at the timing requirements of the dsp an found that for my (...)