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29 Threads found on edaboard.com: Dual Rate
LV7814TA-D Drives two steppers motors DRV8821 dual Stepper Motor Controller and Driver
Hello, I will have to design a dual slope ADC with 11 Bits. Can anyone help me how should find the gain of the amplifier of the integrator so that I can design op amp accordingly. More over I am not sure how to find the range of input voltages which can give a conversion rate of 1k/samples. Thanks Pritha
An LM3900 is a very weird quad general purpose opamp. I have never seen one and I have seen thousands of audio circuits that use audio opamps. A TL071 single, TL072 dual and TL074 quad opamp are designed for audio with low noise, wide frequency response and wide slew rate, very low distortion and very low output impedance (the LM3900 has a high out
Data is coming at 200 MHz and is being read at 100 MHz. The width of the data is 4 bit. Can we put a dual port RAM to transfer the data from 200 MHz domain to 100 MHz domain. Here all the clocks are synchronous throughout the design?
It depends on your clock rate and allowed jitter and distance. dual stripline to RJ45 to Cat5 thru Cat7. Balanced Differential offers the best SNR with good common mode rejection.
If you know the approximate bit rate of Clock A, and Clock B, Can you re-create Clock A from the signal using an XOR to create a pulse for data transitions to re-sync the free-running clock or use a PLL. then you can store the data in a dual port FIFO with dual clock and data with required integrity and buffer size.
The LM324 quad and LM358 dual opamp's are low power which causes them to be slow. They have trouble with high level sinewaves above about 2kHz so a triangle wave above about 200Hz will be fairly messed up. Any half-decent audio opamp like the TL071 single, TL072 dual and TL074 quad work well up to 100kHz so they can produce a good triangle wave up
a Split rail with an option to track or control independently is useful. The efficient way is of course to use SMPS with a single rectified DC source perhaps with phase control and a dual SMPS converter one positive and one negative. The transformers will therefore operate at the switch rate and not 50/60Hz.
When you think about the frequency response of an opamp you also must consider its slew rate at the output level you need. For example, an LM358 dual or LM324 quad opamp with a 30V supply has a gain of about 200 at 10kHz. But if its output level is 20V p-p then its output cannot swing higher than only about 2kHz.
Dear all I am working on Tunnel FETs. When I simulated a symmetric Double Gate TFET, I saw that the electric field and band to band tunneling rate isn't equal in the both channel surfaces. I have written same names for both gates according below: go atlas title Tunnel fet, dual gate, graded HJ (SiG) # mesh space.mult=1 width=1 # x.mesh loc
more precisely a dual clocked fifo
salam alikom all I just want to find any thesis, paper, or any tutorial that shows bit error rate curves for spatial multiplexing dual polarized MIMO for different cross polarization discrimination (XPD) parameters as I searched for them, but I didn't find any thing can you please give me or just send me in a private message any thing related
hi, are the DES and DDR one and the same thing? if the input frequency is 1GHz then the sample rate will be 2GSPS in both the cases.right?
HDL code (a Verilog inout definition) is sufficient. Primitives are only needed for special purposes, e.g to define dual data-rate registers.
Are you absolutely sure that all of the resistors and capacitors on these two boards are identical? Is your circuit operating at a high clock rate? The 74HC123 is a dual monostable multivibrator (single shot mv). Unless the discrete components are different/defective on one board, the two boards should work the same if they are really the same
Hi to all, I am designing a dual channel ADC with a maximum sample rate 22Msps and a resolution of 6bits or 8 bits. Therefore, can any one have a documents about this subject? Thanks in advance
1.25/10.3 Gbit/s dual-rate burst-mode receiver Hara, K.; Kimura, S.; Nakamura, H.; Nishimura, K.; Nakamura, M.; Yoshimoto, N.; Tsubokawa, M. Electronics Letters Volume 44, Issue 14, July 3 2008 Page(s):869 - 870 Digital Object Identifier 10.1049/el:20081295 Summary:A 1.25/10.3 Gbit/s dual-rate burst-mode receiver is (...)
I assume, that you'll use a LUT NCO. For full clock rate, you can utilize a dual port ROM to have sine ans cosine in parallel, for reduced clock rate, the ROM can be multiplexed.
Dear friends In Cover & Thomas book, it is said that the dual of channel capacity theorem (RH), but I am confusing that what is the definition of R (code rate) in Data Compression and also how can I prove that? Is the definitio of R in Data compres. the same as the defin. of R
Hi there, i have some problem while integrating a special dual port RAM core (generated in xillinx ISE) into a Xillinx EDK project. The ports of my DP-RAM are designed differently inorder to increase the rate of data exchange. The DP-RAM size is 1Kbytes. The access on the port A is byte-wise, so the resulting address length is 10 bits (...)