Search Engine www.edaboard.com

# Dynamic Changing

1000 Threads found on edaboard.com: Dynamic Changing

Hello, I am getting the following errors when I run Momentum Virtuoso from Cadence Virtuoso Layout to do EM Simulation of Cadence Virtuoso Layout using Momentum. Does anyone know what they mean or have they ever encountered them ? See below. Thank you. -- WARNING (ADE-5033): Cannot find the environment variable 'write

## Simplest way of converting 240Vrms mains into 450VDC?

Hello. I am building a SPWM Variable Frequency Drive that should be able to output at least 240Vrms @ 50Hz to drive a fan that may consume at most 30W, as far as I know for that I need a DC rail of 450Vdc. What is the simplest/easiest way to achieve a 450Vdc rail? My first idea was a PFC circuit which I used a online design tool to generat

## Design of a linear low-dropout voltage regulator in 0.18um cmos technology

This is my schematic circuit using cadence software. Can anyone teach how to simulate the circuit in transient and ac simulation. Thanks. 151101 Table below shows the dimension and parameter for the ldo. 151102 151103 Figure below shows the dc simulation result but I n

## ANSYS Totem electromigration check

Totem, Voltus (or VoltusFi), or any other EM / IR drop analysis tool simulates current flow in R or RC network (for power nets or signal nets). When it does dynamic EM / IR simulation, a current through each parasitic resistor is a function of time. For each resistor, the tool calculates average current (over time), RMS current, or peak current. Th

## delay of inverters in series

HI I am facing an issue during postlayout simulation where a chain of four inverters is there i have to obtain a min. delay. But when i change the w/l of the transistors there is no change in the delay, it is neither increasing nor decreasing. In prelayout simulation i can easily see the variation in delay while varying the w/l. Any explanation

## HFSS: What on my model is generating this warning?

I designed a model of a patch antenna with circular polarization, but I keep getting this warning when I run the analysis: Model Resolution has caused minor changes in object dimensions or contact between objects. Specific details may be found in Modeler>Model Analysis>Show Analysis Dialog>Last Simulation Mesh. The simulation gets complete, e

## Inrush surge damage to non-pulse-rated 1210 resistor?

Hello, Our contractor has decided that we can save money on our offline 240VAC lighting product by changing the 47R resistor in the attached (partial) schematic to a non-pulse-rated 47R, 1210 resistor. At the moment, we use a pulse rated 47R, 1210 resistor as follows?.. SG73-RT series pulse rated resistor.

## Keysight ADS - patch antenna input impedance (possible incorrect EM setup)

I'm simulating a patch antenna array but I don't understand the output. Keysight ADS LineCalc and Rogers MWI-2019 were used for synthesis and ADS Momentum was used for far-field radiation/pattern simulation. 150913 150914 150915 Here, a single patch was designed, accou

## Transformer core flux

In and ideal transformer all the flux is within the core. So if the flux is contained within the core how can it interact with the secondary winding. Does the flux not have to actually expand out through the layers of windings.

## PWM in Atmega328 using Code Vision AVR

Hello, I have to use all the 6 PWM pins in Atmega328 using codevision AVR. However i am stuck with configuring in Timer0 PWM itself. Below is the simple code with nothing in main and timer0 overflow interrupt and compare match A and B interrupt. Here pins OCR0A and OCR0B are toggling with same frequency though i am changing OCR0A and OCR0B value

## Using a CDL file in LTSpice

I have a CDL file that I'd like to simulate, but I am not a digital designer and do not have access to the tools like Virtuoso or Synopsis. What I do have is LTSpice. Is it possible to simulate the CDL in LTSpice? The CDL has 400+ .SUBCKT statements which would be crazy to try to import 1-by-1 in LTSpice. What would be the best way to go forwa

## ESD and parasitic inductances of bond wire

Yes, short-pulse BVox will be higher, but how much so is something you'd like to know, not take rules-of-thumb. Different ESD "models" impose very different pulse widths (HBM, is more of a RC decay with a fast rise, long fall, and for this case the middle ground wants exploring too - particularly if using a "dynamic clamp" which might release bef

## TSMC 65nm GP operating voltage

Hi, I'd like to study the effect of varying the supply voltage on my design. I'm using DC for synthesis and Innovus for PnR. As far as I know, the supply voltage can range from 0.9V to 1.26V with 1.2V as the default voltage. First, Can I exceed the max. voltage without leakage or logic faults? If yes, by how much? Second, what are the tcl comm

## Reducing quantization noise in ADC with oversampling

hi 1- The below article explains over sampling rate is beneficial because Quantiziation noise contribution is reduced in input signal band with increasing sampling rate . 2- dynamic element matching in flash ADC is done in which reference voltage of each comparator changes randomly with the input of next sample . It is done through random cyc

## HDL simulation help to understand the function of verilog file

Hi, I am writing testbench for a custom axi stream fifo which I have found online. It runs on ZYNQ board but I need to simulate it to understand it's function. In the testbench I have send four packets at slave input s00_axis_tdata when s00_axis_tready is '1'. The signal s00_axis_tvalid remain at '1' during the four packets and there is a s00_a

## About the effect of the PVT process on the LC VCO

I would like to display the frequency variation of an LC VCO with temperature. Hence, i used harmonic balance and options existing in ADS? However, when i put the variable'Temp' as a sweep parameter the simulation doesn't work. I ask how can i use this template to display the frequency variation with temperature ( ranging between 0° and 100°). I'm

## Our header files are static or dynamic library

Hi Everyone, when we create own headers, for istance, math,c and math.h. When we include them, does compiler make them shared or static library. Thank you project : main.c math.c math.h Best regards static or dynamic does not arise when you include math.c and main.c, compiled together to make

## 5 decade precision current sense application

The requested accuracy of 0.1% is hard to achieve with logarithmic amplifiers. Without shunt switching, the overall dynamic of 1e7 causes problems of DC stability, even with chopper stabilized amplifier, and also wideband signal-to-noise ratio is critical.

## RF actuated DC power switch without relay

Hi I am building a small transverter where the power to the TX/RX circuits will be switched, to enable TX or RX. changing of the state of the transverter should be from the RF input (left side) detection. On TX, the (higher than RX) power input to the left side will activate a circuit, to switch DC to the TX circuits. This can be done with a rel

## Measuring transconductance of any circuit

May I know if the following transconductance measurement test circuit is correct ? I suspect that I need to use some