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Dear All, I am trying to generate test patterns for a test bench circuit "wb_conmax" by opencores. I have successfully generated the gate-level netlist. And I had successfully inserted the scan chain. However, I am unable to generate test patterns. It gives following error 157326 The script I am using to generate is as fo
I'm working with the SMP affinity on an i.MX8 system (on a SolidRun HummingBoard Plus) and there are a couple of things that confuse me, but mostly that one of the affinities keeps changing. It's for a timer interrupt, e.g.: root@sr-imx8:~# cat /proc/irq/6/smp_affinity 4 root@sr-imx8:~# cat /proc/irq/6/smp_affinity 2 root@sr-imx8:
Hi, I have a circuit which reads 24V, scales down to controller compatible voltage and controller reads HIGH when 24V is connected, else 0 when 0V is connected. Essentially its a positive logic. 24V = HIGH and 0V = LOW. If I want to convert the same circuit to a NEGATIVE LOGIC i.e 24V = LOW and 0V = HIGH, what would be simplest way without chan
I am doing a automatic water level controller using PIC18F46K22 which also monitors mains voltage and pump current and controls the Pump. I thought it is better to implement dynamic dry-run and overload current calculation method. So, Can I implement this method in the code? Target = 2-HP Pump, 1-Phase, 220V, 50Hz
Hi guys, I designed a PLL, and I'm not getting to a locking state yet. I'm trying to debug the problem by observing the behavior of different signals. It seems that I'm getting only Up Pulses and the behavior is periodic. here is one that simulation that shows the periodic behavior of Up pulses: 157210 [ATT
Hi, From the view of antenna theory, beam forming means using multiple antennas to create a desired beam, or controlling the beam direction by changing the magnitude and phase of each antenna element. Usually we'll regard all the elements as one antenna when we look at the far field. In communication theory, MIMO means utilizing diversity to
what does the rule you want to apply in your system ? This document offer 2 methods for choosing pre-amp: prioritize sensitivity or dynamic range. If your receiver near transmitters, ( including noise from other transmitter) the signal input too strong, it can make your receiver saturation and total gain would be decrease. You must chose pre-amp w
Hey guys! This is my first circuit I build, so please bear with me. I made a prototype for a dynamic mic amplifier on a transistor and LM386 which contains a transformer and 4 electrolytic capacitors (and some others for bypassing and filter - 1n , 100n). Electrolytic ones are 100 uF and 220 uF 16V. The source voltage is 9V. The prototype
Hi the manual for the Yaesu FT-101 says it expects a high impedance dynamic microphone. The schematic is attached. Now I have a dynamic hand mike and when I measure the resistance of the mike element it shows 500 Ohms. Is it considered a low impedance capsule or high? In any case, can I use it with this rig? I suspect there will be no real proble
Hi Everyone, I have designed a NFC system in which I can have around 100 V on the input antenna. So I need to attenuate the antenna signals (in terms of mV) before feeding them back to the reader module as well as keeping the antenna's resonance circuit quality factor. Hence, I would like to know an attenuating buffer circuit for my applicat
HI, i need some help on this simulation. can someone tell me how fix de error "Timestep too small", or review my schematic. tks
Please help me to find total,dynamic,leakage power dissipations in a simple inverter circuit using LT Spice XVII
Hi, I would like to generate a spice netlist from Cadence Schematic. I have googled and found comments saying using HSPICE simulator which is not working for me. Is there another way to generate a spice netlist from Schematic?
Dear friends, I have designed the same circuit shown below, . the circuit use two common mode feedback circuits, the first one that adjust the common mode voltage between o1p and o1m while the second one is not shown but it is contrroling the output voltages vo1 and vo2. I have no issue of the outer common mode voltage as the common mode vol
Hi All In my design D is changing just before clock edge but there were no violation reported. I know it is because of massive hold violation because launch clock is coming early and capture clock is coming because of which data slippage is happening. Can anyone help me what exactly happening here. Also why can't it be setup violation? Thanks
Hi all, After reading many posts in the forum, I started to get confused. My understanding on metastability is it cause the output to be X. This mean it can be any values. By having high MTBF, we have high probability to avoid metastability. My question is does this mean we will have a correct output value? Or it just won't be intermediate va
hellow guys iam writing a simple bootloader on a stm32f103ve microcontroller from address 0x8008000 and a userapp code from address 0x8008000 my bootloader code include uart1 configuratin for show some massages and spi2 configuration for communication to a spiflash and my userapp code include timer6 , timer 7 configuration for two led blink wit
Hi, i designed a sinusoidal pwm amplifier (3KHz to 20KHz) that regulates its output voltage reading the RMS value of output current. The RMS is obtained squaring the signal sampled by AD converter @200KHz and then applyng a FIR filter with 120 TAPS. The advantage of this method is that the settling time of the FIR (so the response to amplitude c
In the circuit, I want to compare the voltage reference Vref and source voltage Vdd. It is necessary to make Vref change with Vdd, which means a constant voltage is supposed to connect between this two voltage. But I have no idea what structure can achieve this.
In the circuit, I want to compare the voltage reference Vref and source voltage Vdd. It is necessary to make Vref change with Vdd, which means a constant voltage is supposed to connect between this two voltage. But I have no idea what structure can achieve this.