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Hi, I have a MCP6002 wired as a buffer circuit. A voltage divider with 1M and 20K to ground. When i feed the voltage divider output to input of the buffer. The output voltage of the Buffer when measured is off by few milli volts, and it changes at various voltages of the input. The input voltage was always well below the max Supply voltage of
I am able to import the HFSS model into circuit view, create a matching network, see how much return loss and coupling I have through the circuit analysis results. However, I am not able to see how the matching network changes the realized gain. I could do a "link output" for the gain, and multiply it by (1-S11^2) in the circuit results, but tha
If i put this statement (state_nxt = state;) at the very top of the always_comb, the default statement in 'case' is not required for it to not synthesize into a latch. Is this correct? Would you still put the default statement for simulation purposes and why? always_comb begin state_nxt = state; case (state) ..... ...
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What is the best way to make a sign wave shift frequency downward only about 10 Hertz, then repeat every .2 seconds. The initial frequency 3000 Hz. There will be 2 generators sweeping, both will be in sync (repeat at the same time). See attachment for drawing.
What do you mean with "dynamic"? Parameters are fixed at compile time, or in usual Verilog terms static. Please note hat my parameters will not be static, I really want to change it a lot to generate different scenarios. For example, if I changed NUMBER_OF_B to 4, I would like to have the parameters C1 shifted in values as wellI d
You do fundamental errors.. -DC OP gives you "static" intrinsic parameters, not dynamic..Briefly it computes intrinsic parameters for given DC OP. -s-parameters relate the Input and Output to "small signal" Transfer Function under the condition Ports are terminated by Zo, so intrinsic parameters cannot be accurately extracted with s-paramet
In IC6 Go to - Options -> dynamic Display Turn on info balloon, select desired info, apply, hover cursor over path. It should then display the path length
Can someone please help me understand the approximations that are made in this attached handout. In calculation of rise time the Q is assumed to be off but in reality it is in active region ? Second, in calculation of fall time , Q is assumed to be a constant current source but in reality the current is changing ? Thank you
Why don't we generate Phase Interpolator using RC Delay ( LPF). Just by changing the R/C Value, delay can be generated and it can be go through a comparator or Strong ARM to get the suare wave with Delay based on digital code.
Hi, I'm using Calibre in Cadence Virtuoso to verify my layout using Silterra's PDK. I have acquired all four DRC and LVS/PEX runset and header TXT files, but all of them could not be loaded inside Calibre Interactive. Below shows what would happen after loading the DRC runset file after being prompted to do so: 155501[/ATTA
DNL This is a static DNL. Evaluation of static DNL and INL does not require Histogram. On the other hand, dynamic DNL requires Histogram.
Hi guys, Can anyone tell me what kind of antenna in some key fob. As i can see, it is just a trace which is 7.5 cm length (the frequency 315 MHz) I attach the image of keyfob below, can anyone explain to me how it work and some related formula to design with another frequency. Thanks. 155433 155434[/ATTA
155372 Hi All, I am designing a reference circuit for the current steering DAC. The current provided is 10 uA and I need a current of 500nA as LSB current. I decided to take up PMOS based DAC with nmos cascode current mirror as its reference (as shown in the figure). I was able to achieve the design working u
By default most digital blocks in CppSim have an output between -1 and 1. I want it to be between an user-defined fixed set of values, for eg. 0 and 1.8. Till now I have been using a multiplier followed by an adder for primitive blocks(eg. xorpfd), or changing it in the code itself for non-primitive blocks (eg. vco). Is there any other way to do
155384 I made a device which uses 18650 battery for runing RTC. A coin battery was not possible because the customer did not want the hassle of changing batteries for at least 3-4 years. The 12v is converted to 4.2v (because there are some other things on board which run @4.2v) I connected the VBAT pin of STM32F103 dir
INL and static DNL are evaluated by ramp signal drive. dynamic DNL is evaluated by histogram for sinusoidal drive. Before EDA Tool Play, learn how to evaluate ADC by using actual instruments. See
Hello all! I'm pretty new to ASIC and liberty files and I was wondering if there was a general trend in liberty files and different threshold voltages. For example, say I'm operating on a library (I'll try to make it as general as possible so std cell, io or memory - any cell, any PVT) and the only variable that would be changing is the thres
Is there a way to simulate s-param changing tapping point of M-Line in ADS? I've tried with two M-Lines and putting terminal in between but wondered if there is a better way to simulate the circuit. Thanks in advance.
Hello, When I run lvs I get error : mismatched instance subtypes and description is : layout instance of X1407/M2 MP(pch_alvt_mac)| Schematic Instance: MM1==17(pch_lvt_mac). Is this some kind of connection error? I have already checked vias and it seems that everything is connected correctly. Should I double check it? It would be very help