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Hi I want to design a comparator with varying hysteresis. What are the important parameters that should be considered while setting hysteresis? How can the hysteresis be modified? Thanks Rati
A microphone has a tiny output level of about 10mV when 10cm away from your mouth and you are talking at an ordinary conversation level. A preamplifier with a gain of about 100 to 300 is needed for the preamp to drive a recorder or a power amplifier. There are a few different types of microphones: 1) dynamic, has a coil and magnet like a little lo
Hi, I set Width(W) and Number of fingers (nf) for a transistor (in CS configuration) and found out it's drain current (Id) and output power (Pout)(Using HB simulation) for a particular load resistance(R). Now, If I want the output power 8 times that of Pout, is it just enough if I take 8 multipliers without changing R ? and does that mean Drain cur
Hi, I am currently designing an ring oscillator of 100-200 MHz frequency, and have to measure the absolute jitter using transient simulation. The schematic consists of a 5 stage ring oscillator and an ideal voltage source of 1 V to power the osc. A jitter was measured using abs_jitter function, which is a built-in function in the calculato
Yes, you need to use a VCD file, otherwise the toggle count used for the power estimation is just a fixed value, and is unlikely to be the same as in your design. As dynamic power is proportion to the amount of toggling, this can result in widely inaccurate power estimates. You can read a VCD file in to Design Compiler though. (And it's worth doing
you can't easily have current mode control with HB - so if you are seeking a tight dynamic loop - FB may be the better option.
Hi, I know how to find dc analysis (to find gm) and ac analysis (to find gain) for a given circuit (Say CS stage) when resistive load (say R)is there, i.e. Resistor is connected between Vdd and drain terminal. From this I can arrive at the conclusion that voltage gain Av=-gm*(rds//R). 154326 But what happens if I have
I do not understand why the author claims that his dynamic divider circuit is "speed-optimized" ?It is very natural nature of dynamic circuit. Small size can not work for slow clock.
I appreciate it isn't easy to photograph a dynamic display but it would help if we could see the problem. Note that the maximum current available from any PIC pin is 20mA and there is also a limit for the port as a whole, you might be exceeding it. Brian.
If it was a dynamic testbench, Id say you have a delta race. Ie. reset_wsync is dropping just before the clock edge, hence it thinks a write has occured (because reset_wsync has actually dropped already). For formal, Im wondering why you have asynchronous reset asserted at all. Have you made assumes for it? Is this wave a counter-example where your
Thanks for your suggestion. As my total projects (Isolator is one part of the project) are connected via dynamic link feature of Ansys, therefore I need to have some guidance on Ansys. Besides, in my lab, we have the flexibility to use Ansys and Comsol only. No ADS or CST.
Hello, Do you know why this LTspice simulation of a synchronous 2 transistor forward converter using LTC3705 and LTC3706 won?t even start switching the fets? LTspice sim and scm attached LTC3705 datasheet LTC3706 datasheet
I have a LG 22LG3000 lcd tv. Problem: it was working fine then it suddenly said 'no signal'. I turned it off, when I turned it back on I got the welcome screen and setup wizard. I went through to autotuning, it searched but no channels were selected. I exited the wizard and it said 'not programmed'. Any ideas appreciated. Thanks.
I don’t know what postprocessing tool you use. However almost all postprocessing tool have ability of X-Y plot. Use X-Y plot. If you prefer static load line, do DC analysis. If you prefer dynamic load line, do transient or pss Analysis.
is it possible to measure the parasitic capacitance at a certain node in a schematic in cadence??I don't know what you want to mean by "in a schematic in cadence" at all. However Synopsys HSPICE have following. .OPTION CAPTAB Adds up all t
I want to make a RTC clock with 4-digit 7seg disp which will display " HH:MM " in multiplex tech. I have 4 nos digit and each are of CA type. As the each single-digit has one DP and which is located on right side of the digit. As of " HH. " (H-ten, H-one , .Single Dot) is Ok and I have no problems, But to get one more Dot on upper portion to fo
hello Guys i have got a new board STM32F103C8T6 Which named Blue Pill i did all the instructions for uplading a program on it using usb to serial adapter but Arduino IDE give me errors Sketch uses 12648 bytes (19%) of program storage space. Maximum is 65536 bytes. Global variables use 2456 bytes (11%) of dynamic memory, leaving 18024
Hi, I designed a power amplifier, it has some power gain (Ap) and bandwidth(BW) after perfectly matching at input and output. I want to know 1. How to increase the Ap without changing BW? -I know the below case but I would like to know if there any other ways a) By increasing transistor widths, I can increase gain -- but in this ca
when i run the LVS for my circuit, the layout extractor translates the resistor layout i placed- rnwsti(2 pin) as rjnwsti(3 pin). so i can't pass LVS. anybody have any tips on how to fix this? i am pretty sure source side of things are perfectly ok.
Hi, from the headlines - I assume every document on the first page should give useful informations... Klaus