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19 Threads found on Dynamic Comparator Design
hello guys. I just have desined a SAR ADC with a 12-bit resolution and 1mhz sampling rate. but i find some problem with it : when i simulated the ENOB with it and i found the enob droped when the frequency of the input sinewave rises. can anyone tell me why this happens and how i can make it solved? thank you all!
Is there a design methodology one can follow to design a conventional dynamic comparator? 133900
Pretty simple design. Precision OA peak detector with variable gain. Selected dynamic filter, amplitude controlled envelope to comparator. with PWM 1. fast attack , slow decay, 2. auto ,max peak and hold controlled brightness with slow attack and decay. 3.same as 1 except trigger advances MUX'd output on leading edge 4 (...)
Hello all; In pipeline ADCs where charge distribution dynamic comparators are used, the design of the different comparators is the same, they are only fed with different references to make them get exercised at different input voltage values.....When applying a ramp to the ADC each comparator exhibits a (...)
Hi, I am a beginner for analog circuit design. I try to design a dynamic comparator, schematic shown in figure. Single supply voltage Vdd=1.8V, (Vcm=0.9V), 0.18um cmos technology(600MHz frequency). I have following question: 1. How to size ration nmos and pmos in this circuit? Any reply will be appreciated. Thank you (...)
hi i am a beginner in analog circuit design.. I am designing a dynamic comparator for pipeline ADC in 90nm Cmos technology shown in the figure.. 1.8V supply voltage(Vcm=0.9V).. This dynamic comparator is to be designed for 2.5 bits flash sub-ADC.. I have several (...)
in dynamic comparator design of differential pair, i have some questions here. 65665fig1 is the schematic, fig2 is the design equation. d=ID5/ID6, e=Vin/Vref, W1=W2, W3=W4. but how to decide the value of ID5, ID6, d? because M5 and M6 are controled by clock signal Vclock, so the current of M5, M6 is difficult to set
1) use transient simulation 2) use dc sweep input voltage 3) dc sweep 4) quiescent current with dc sweep. transient simulation for dynamic power
Hi all, I'm using sense amplifier based comparator in my ADC.please post some reading materials explaining various aspects (and design)of comparator like dynamic offset,mismatch,parasitics,hysteresis etc., This is the
in my project we have to design dual tail latch compaparator... i want something about dual tail latch operation
if you want to save power you should use dynamic comparator, but it can have really big offset ~100mV , and you will not be able to simulate all effects... problem is that offset is usually not constant and directlly affects on adc performances... comparator has to be much beter than 8 bits... if you want to achieve 8 bit adc resolution...
hi there, Does anyone know why is dynamic comparator (rather than preamp+latch) frequently used in pipeline ADC design? what is the advantage of it compared to other structures?
am not able to increase the gain of the pre-amplifier stage beyond 2V/V. is this gain sufficient for the design. gain is low because the load for M1 and M2 transisters are in trode region(according to the design). how can I design the dynamic latch.
hi, I believe Vref+,- are decidec by application, or some external restrictions, not your circuit. They are inputs to your circuit. if you remove the most upper left PMOS, the most upper right PMOS, the most upper two NMOSs, there will be two inverters left. They form a latch up circuit. The sizes are up to the DC current, switching speed...
use dynamic comparator
Now I design dynamic comparator for pipeline ADC. But there are some is my design parameter. Vdd = 3.3V (CM = 1.65V) Vref+ = 1.9 V Vref- = 1.4 V Vin+ - Vin- ; ramp signal from -3.3V to 3.3V 1. This comparater generates 1/4Vref threshold voltage if I design W2/W1=0.25.
I am just a begineer in analog circuit design.I need help for dynamic comparator in pipelined ADC.I have two DAC which is connected to ADC which composed of two dynamic comparators. Whe I test them seperately,they works fine.But when I connect DAC to ADC, the output from one DAC is not correct.I search (...)
I am designing a 8bit 100MHz Pipeline ADC, and the result puzzled me. The structure is 1.5bit/stage *5 + 3bit/last stage. The result is that 1Lsb is always wrong. Can someone give some advise ? Or point some key notation? Additions: In this design, there are a S/H circuit, gain stage(include OTAs), dynamic comparator, and (...)
Hello! I need to design a dynamic clamp circuit for about 5V. I need it because there is an internal regulator with PMOS in my IC and when a big positive step appears on VDDext, VDDint jumps for a while and could destroy the core cells. I dont want to use static clamp because VDDint is also almost 5V and this could cause problems.