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# Dynamic Performance

47 Threads found on edaboard.com: Dynamic Performance

## simulate DAC using SIMetrix

Hi all, does anyone have any reference about how to simulate DAC, especially using SIMetrix, to check its performance both static and dynamic? thanks, regards

## ADC problems need help- static, dynamic parameters get worse

for a pipeline ADC, 10-bit 10 Ms/s, if a sine input signal is aaplied in the input-end, then we can get the dynamic and static parameters by simulation. i want to ask, with the increasing of input sine frequency, both the static and dynamic parameters get worse, why? which reasons can cause the performance decline?

## How to evaluate the chip's Qor of the P&R

There are different metrics.. * performance * Power (leakage and dynamic) * Area * Run time of the implementation.

## Two tone simulation for determining the dynamic performance

hi, i am planning to do a two tone simulation for determining the dynamic characteristics of a Pipeline ADC.Can anyone can giv m some idea on this...

## how to chose the input freq for dyanamic meas of ADC

i need to meas the dyanamic performance of ADC what input freq i should chose to calculate the dynamic perf my sampling freq is 4msps

## Testing INL/DNL on PCB using ramp signals

add a ramp signal as the source signal. waht's the relation between the freq of ramp and the freq. of sampling? i means what freq of ramp is suitable for testing the static performance . and what about the freq of sin wave for testing the dynamic performance, what's the coherent freq?

Hi To evaluate the ADC dynamic parameters like SNDR, SFDR, ENOB etc, we usually apply a full scale sinusoidal signal at its input. Can any body tell how can we choose the frequency of this sine wave?? I request for a detailed explanation.. Thanks a lot.

## How to measure the performance based on the Matlab model?

Hi , I am realizing a digital IF system with a FPGA and I have construct a model for it with matlab/simulink. The problem is that I don't know how to use the model to measure the performance of the system, such as dynamic range, the impact of fixed-point realization on the system performace. Would you like to give some idea? Thanks.

## How to measure the DC noise?

to know the amount of the noise and it's spectral density You may use the FFT Analyzer ( also called dynamic Signal Analyzer or Low Frequency Spectrum Analyzer). To know how much the noise is "white" and gaussian You have to sample, store and then perform the Allan Variance

## Standard for DAC characterization (static and dynamic performance)

Is there any standard for DAC characterization (static and dynamic performance)? IEEE has developed one for ADCs. (IEEE Std 1241-2000) (IEEE STANDARD FOR TERMINOLOGY AND TEST METHODS) Many textbooks focus on DAC characterization after fabrication. I am interested in a methodology for characterizing the performance on schematic (...)

## Do we have to check INL/DNL?

For a converter design, how does the static performance (INL & DNL) affect the dynamic performance? Of course a bad INL or DNL will lead to a inferior SNR and THD. But if the dynamic performance is checked and proved by the Monte Carlo transient analysis, is it still necessary to check the static (...)

You can use the clock tree format to drive the comparators. But you need to carefully take care the layout matching issue. It will affect your dynamic performance in such high frequency. Usually, the inverter size is like 1-->3-->9. Yiibn.

## Audio (16bits) band sigma delta ADC reference decoupling

Hi all, For this kind of ADC, you need 3 references: positive, negative, and analog ground. Does anyone know for a 16bit dynamic range performance, do you need off-chip decoupling of the above references, or on-chip bufferring/decoupling is enough? Thanks in advance! CC

I use a piecewise linear approximation to achieve logarithmic function. When I simulate the RSSI transfer curve, the dynamic range is very low. I think it is due to the poor performance of Full wave rectifier. How can I know that the full wave rectifier(FWR) is good enough? according to the Katsuji Kimura paper, the input range of our FWR is fr

## what kind of test needed to characterize the LDO regulator ?

hi, include static performance such as load regulation,line regulation,dropout voltage,quiscent current consumption.dynamic performance such as settling time,overshoot and undershoot voltage, etc.Frequency performance psrr is very important also. Additionally,you must assure your LDO is stable.

## How to improve the system performance of ad hoc networks using neural network?

hi i dont know much about neural networks...i present here some vague ideas... ...but there are some issues in ad hoc networks that can be dealt well with neural network fundas... * dynamic MAC * security in MANET * maulticasting * and with neural network concepts u can think of developing a new routing method like routing based on battery b

## Sample & Hold ENOB Measurement problem(INPUT pulse).

Usually SHA is used in together with the following switched-capacitor circuitry for further processing ( a good example is pipelined ADC). Thus, FFT analysis is definitely useful if you pay attention to where and when to process the data. The pulse response is useful, but it does not provide full picture of the dynamic performance of the SHA.

## DSP Based SoC Static/Dynamic Timing Analysis

DSP Based SoC Static/dynamic Timing Analysis Using PrimeTime/PowerMill Yaacov Kobrinsky, Eli Ofek DSP Group, Inc Israel ABSTRACT Our DSP based System On a Chip (SoC) is aimed at achieving the best cost-performance for a given silicon area, taking into account memories area size (ROM/RAM), ?glue logic? (ASIC portion), smart power management