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47 Threads found on edaboard.com: Dynamic Performance
It's been a few decades since I worked with these types of A Law Codecs. TI user forum may be helpful too. Good performance with synchronous conversions and wide dynamic range high SNR in 8 bits with 4KHz BW and 8KHz sampling rate, which includes S&H and 5th Order Nyquist filter and sin x/x correction with 5mW driver.
I have to do simple numarical simulation. I'm stuck there. I have to compare normal GPS receiver tracking performance and Ultra tightly receiver tracking performance.I have to use tracking error equations (for Thermal error, dynamic error for Costas PLL and DLL)for both receivers and get some graphs and compare..The attacments are the (...)
At first Fn ( or T, equivalent noise temperature ) and linearity. Linearity that is input P1 IP3 and as function FEM dynamic range. Mirror channel selectivity if necessary performances of the preselector filter. And third all kind in and out unwanted channels and emissions. It is very briefly.
dynamic range in the energy meter specification means current dynamic. Voltage will be nominal mains voltage plus/minus expectable variations. As a result, all current spectral components except a small band around the fundamental will be filtered out when multiplying current and voltage and integrating over full 50/60 Hz periods. Low-pass filterin
Could use some background information on designing a common base amplifier for High dynamic range performance (IIP2>+80dBm). I read some articles, but would like to know if some of you have some hands on experience with this topology.
Hello everybody Can anybody please tell how to calculate dynamic performances for a DAC with simulation (by Cadence for exemple) ?? Thank you in advance
hi all, kindly, i make sar adc 8-bit and i wanna measure its dynamic performance to calculate ENOB , my max i/p frequency is 574K and fs=2Mhz i choose Nrecord=2048 and Nwindow=585 so fin=573.3K , is this true and what's exactly method to know i.p sinwave needed in fft? thx in advance
A system-level solution would be to implement dynamic voltage and frequency scaling, which would require the designer to characterize the ASIC across a supply voltage and frequency range. Foundries supply mult-Vt devices, based on your power/performance target, choosing the the correct Vt devices for your design (one or more) is crucial to limit l
I have designed the SAR ADC of 8 bit with sampling frequency of 1MHz in cadence.For calculating the dynamic performance , i have used code provided by Maxim . for exporting data , i have used the tool called TABLE in cadence and saved as . csv file and for processing , i deleted the time and heading of Table and saved as txt file and fed to the mat
As long as radio communication uses small to medium relative bandwidth, down- respectively up-conversion before AD/DA processing will most likely offer performance benefits at least starting from VHF bands. Frequency conversion isn't a big thing. IF bandwidth and dynamic of digital receivers marks the progress. As it increases, direct digital "UWB"
You should repair the MT-077.pdf link But chuckey has explained the reason for better performance of transistor log circuit, also without the link. In addition, I don't understand the below expression related to the discussion. dynamic range of a log amplifier refers to input rather than output signal. A dynamic of 120 dB (6 decades) (...)
It's quite obvious, that the incremental realloc() will be basically slower. It's only advantage is not needing to estimate a file size. In a real world, the decision would depend on parameters like: - single or multi-tasking enviroment - maximum file size - static or dynamic (e.g. swapping) memory resources - performance objectives
Hi, Usually, for SD standards(NTSC,PAL), the video's signal bandwidth(BW) required is 4MHz. This goes upto ~30MHz for HD standards(viz., SMPTE274). The video signal is normally pre-processed in 8 bits for SD standards. Hence, the expected ENOB from the DAC is 8 bits, which translates into an SNDR/SINAD
hello every one!!! what is the formula to calcultae the performance of the ΣΔ adc? is performance and dynamic range same for a sigma delta adc???? ---------- Post added at 07:00 ---------- Previous post was at 06:07 ---------- is performance equal the SNDR of the ADC??
Pout is relative low, why that big attenuator then? 20dB attenuation => 20 dB reduced dynamic range of VNA. How much power can your VNA handle? Measure TX impedance requires that the chip can be set in CW mode, I assume? Measuring VSWR of antenna do not result in impedance values? What type of VNA do you use? Measured TX out power level can be impr
Yes,capacitor load condition will influenct high frequency performance. For example, PSRR at 1MHz. Thank you leo_o2!! Can you please elaborate on dynamic performance? Are they the charactersitics that varies over frequency, like PSRR, gain, CMRR etc? Thanks a lot in advance!! M -----
Improving performance for dynamic memory allocation
recently , i'm testing a sar adc . an arbitray wave generater or an active crystal as the clk signal of the adc in the test board. and foud the dynamic performance of adc using active crystal better than that using the former one. so how to improve the test results by using the AWG .?(50 ohm res in the board as the load of AWG)
I have an inl & dnl simulation code by Matlab as the attachment, but I think this file isn't effective. Because I have to input sine and ramp signal to get the performance of dynamic (fft) and static (inl & dnl) respectively. By using LA (logic analyzer) in testing ADC, we just need to input sine wave andv then get the dynamic and (...)
Hello, Something just popped up my mind. How to measure/display dynamic performance (e.g SFDR) of an ADC as a function of input signal frequency and input signal amplitude? Thanks in advanced