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34 Threads found on edaboard.com: Encounter Buffer
Hi, As the title of this topic indicates, I want to synthesise and P&R a design without buffers in order to observe the behaviour of long interconnects to the delay. Therefore, I want to know if there is any way to disable buffer insertion to my design, both at the stage of synthesis (Design Compiler - Synopsys) and the stage of place and route
Hi While doing HFNS i got the high fanout nets using the dbGet command. but when i give buffertree synthesis command it says, two nets have no driver so It shows an error message and it aborts the buffer tree synthesis operation. The net it is telling "no driver" is actually a pin of macro. Do i need to give any special command?
Is there any command in Cadence encounter that will display a cell's or buffer's properties like delay, slew, fanout etc.?
Hi, I am new to SOC encounter and I am using First encounter. When I try to do the physical design flow, I am having setup violations after nanorouting stage. The violation remains even after optimizing the design. I've read that addition of buffers will resolve the issue. But how can I add buffers in the design?? How (...)
Hello sir , can you tell me how to find worst case delay of combinational logic or critical path delay of combinational logic in encounter RTL compiler. can you tell what commands to be used?????
I have inserted integrated clock gate cells in my design in DC and during clock tree synthesis, encounter inserts the CLK buffers before the clock gate. This causes the buffer to run, when there is no clock required. ANyone know how to move the clock buffers after the clock gate cells, so that they switch only when the (...)
Hi, I'm designing a Delta Sigma modulator, and synthesizing it using SOC encounter. When I design the clock tree and choose the buffers and inverters to be used, encounter always choose the largest buffer as the first stage, which shouldn't be. the later stages are smaller!. Is there a place where I need to set the (...)
hi... I have to place layout instances (ex: buffer with pins in, out, vdd,vss) in encounter..I have no netlist regarding these instance..But I have mentioned in LEF files about that instances..What command I can use to place these instances in encounter... If anyone knws help me plz.....
For clock, just let the encounter do it using these commands: createClockTreeSpec -output clk.spec clockDesign -specFile clk.spec ckSynthesis For reset if you want to buffer it, make a copy of the clock spec file and change the clock name to the reset name. Then use these commands: clockDesign -specFile rst.spec ckSynthe
Hi, When I'm importing my Design to SoC encounter, in the log it says "list of usable buffers: ..... and then list of unusable buffers: ....". The thing is i never ordered the tool to avoid using a buffer (aka 'dont_use'). I checked the SDC file, no such statement. Why then it prevent the using of some of the (...)
Thanks for your answers. sam33er, any idea how do i do that in SoC encounter? didn't find that option. huckle, i can select the net, but how do i insert buffers manually? (i am pretty much a beginner) There must be an editor tool to do this. you can cut the net and insert the buffer there manually.
Dear all, I want to build buffer tree for signal RESET like other clock nets,as so many max_tran vios occurred on this net under bc condition. I add clock constrainst (skew,latency...) into clock spec file and then do CTS,tool reports that,clock net RESET does not have syn pin,and can not trace clock ne
It's normal practice to put invertor/buffer into scan chain. When you load test vector in chain ATPG tool knows that values will be inverted on such invertors. The same happends when you unload captured test vector. You shouldn't generate test vector by hand. Use TetraMax (FastScan, encounter Test...) for automatic generation. Tool knows about this
There are many pins in the Hard macro,and per pin connects per buffer, I want to place the buffer near the connected Hard macro's pin, In Astro ,I knew the command "astMagnetPlace" can do it! But What can I do for it without setting region in Soc encounter tools.
I have one question How does encounter recognisez whether a cell is of delay type or buff. In my case BuffD1 is buffer where as BufD8 is delay. ######encounter.log List of usable buffers: BUFD1 List of identified usable delay cells: BUFD9 ################################### I checked Lef files and the lib files but (...)
But if you want to balance the skew. Simple option is to use the CTS algorithm, instead of specifying clock, specify the HFN net & encounter will build the buffer N/W to meet the specified skew requirement. Could you elaborate on that? In encounter, if I have a signal (output of a previous DFF register) which needs to f
I get this error when I try to synth clk in GUI: Tracing Clock uPAD_MDQ_clk/OY ... *** End Tracer (mem=129.8M) *** **ERROR: No sync pins are in clock uPAD_MDQ_clk/OY. Please remove it from clock spec file. This is how I created the clock in SDC: create_clock -name {IO_MEM_NPL_MDQ_Y_clk_} -period 20.000 -waveform { 0.000 10.000 } [list [get
Iam working with soc encounter 8.1 I have a bidirectional buffer in vhdl as follows ----------------------------------------------------------- entity bidirectional_buffer is --generic (width : integer := 8); port (y1 : inout std_logic; a1 : in std_logic; e1 : in std_logic; b1 : out std_logic); end (...)
HFN constains three type: 1.clock 2.reset 3.general purpose solution: 1.set_ideal_network (-no_propagate) or set_dont_touch_network 2.set high_fanout_net_threshold,high_fanout_net_pin_capacitance when use dc,then insert buffer wen APR use Astro or encounter a paper of SNUG
I am testing a chip of a clock circuit. At first it works normally,but later on I found the output(of a chain os inverter buffer) is appear as an DC clamped at some 1.9V.(Vdd=3.3). I also notice that the clamped voltage is changing according to Vdd. In the chip I did no ESD for the output inverter buffer. So anybody ever encounter such (...)