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148 Threads found on edaboard.com: **Equal Gain**

Hello Friends,
I am designing a Charge sensitive amplifier and would like to study about the stability.
we know, A/1+AB where AB is the open loop **gain**. If AB is **equal** to -1 then the system will oscillate. How would I know that AB will be **equal** -1. Please tell me the process to calculate.
A= G sCdRf/ 1+sRf( Cd+Cf)
B= (...)

Analog Circuit Design :: 02-28-2017 13:55 :: tisheebird :: Replies: **0** :: Views: **1**

GBW of aux opamps has to be **equal** to dominant pole of main opamp. In other way You get zero (if GBW is lower) or additional pole if it is higher.
It results with auxilliary amps dominant pole location **equal** to main opamp dominant pole divide by aux opamp **gain**.

Analog Circuit Design :: 12-20-2016 17:56 :: Dominik Przyborowski :: Replies: **5** :: Views: **1263**

Hello, I had a question in op amp?
If we provide **equal** dc voltages to an op amp it will produce some voltage 'Veq'.
The op amp has a finite **gain**. My understanding is, if we use this circuit in a negative feedback loop of another circuit X, its input voltages come closer to each other.
However they do not necessary become exactly **equal**. I (...)

Analog Circuit Design :: 09-27-2016 06:15 :: Debdut :: Replies: **1** :: Views: **569**

Equation 23, page 14 , of AN57 by power integrations (below) shows a parameter called
?K TL31? which is the **gain** of the TL431.
From the attached TL431 datasheet , does this **gain** **equal** ??.which **equal**s 1/0.0014 = 714
TL431 datasheet:
AN57 by Power Integr

Power Electronics :: 02-28-2016 13:27 :: treez :: Replies: **8** :: Views: **850**

How OPAMP ensure both input terminal are **equal**?
Simply using negative feedback ??
Thanks

Analog Circuit Design :: 12-14-2015 20:18 :: Ltarek :: Replies: **2** :: Views: **490**

Yes, that means the op amp will be unstable if used as a +1 follower.
A minimum closed-loop **gain** of +2 for a non-inverting amp or a **gain** of -1 for an inverting amp is the same from a loop-**gain** point of view since in each case you have two **equal** value resistors going to the op amp (-) input.
The only difference between the (...)

Analog Circuit Design :: 12-09-2015 20:02 :: crutschow :: Replies: **3** :: Views: **543**

Normally all values are **equal** for a unity **gain** differential amp ( 10K) to minimize offset from input bias current.
inverting **gain**= -R7/R8 *7V = (-1) * 7V
Non Inv **gain** = 1+ |inverting **gain**| * V+in= (1+1) * 5V*R5/(R5+R6)= (1+1) 5v * 1/2= 5v
Using superposition rules the output-7+5 =2 the difference.
As a (...)

Analog Circuit Design :: 07-30-2015 20:45 :: SunnySkyguy :: Replies: **4** :: Views: **1028**

Where do you see doubled current, in which situation? In steady state, the inner loop current setpoint must be obviously **equal** to output current, are you talking about transient states?

Power Electronics :: 06-25-2015 22:19 :: FvM :: Replies: **7** :: Views: **715**

In open loop configuration it's enough to use a single pulse source in series with one of the Vcm bias supplies (small signal stimulus).
In closed loop configuration (your application) you better use 2 **equal** anti-phase pulse sources in series with a common Vcm bias supply and (if so) the **gain** setting input series impedance d

Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 04-09-2015 19:53 :: erikl :: Replies: **1** :: Views: **752**

hello everyone...
is it necessary to have the UGB of single ended differential amplifier used as CMFB of main opamp to be **equal** to the UGB of the main opamp ????
Is there any specific crieteria???

Analog Circuit Design :: 02-12-2015 15:03 :: pankaj jha :: Replies: **1** :: Views: **747**

It seems that you should use linear values for every specification. The reason 1 is subtracted from NF is because it is always greater than one in linear scale. Therefore, that performs is just how much better than 1 your design is. The same goes for the **gain**, if you double the **gain** while maintaining everything else **equal**, you should have (...)

RF, Microwave, Antennas and Optics :: 12-20-2014 07:43 :: csolis_GT :: Replies: **10** :: Views: **1208**

The loop **gain** at DC is 90dB. However, my PSRR at DC (taken at the top of the resistor) is 80dB.
Does this make sense? I would have thought the PSRR at DC should **equal** the loop **gain** at DC.
There's no direct connection between open loop DC **gain** and PSRR at DC (better: at low frequencies: DC is static, no cha

Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 12-11-2014 20:47 :: erikl :: Replies: **2** :: Views: **819**

You can use a positive bandgap reference of any voltage and your negative supply scaled to be **equal** and opposite. Then your inverting input is now 0V ,( with +Vin=0V) your (-) must now use the same source impedance with a common feedback **gain**.
You may add series RC values for derivative and proportional **gain** control and common RC (...)

Analog Circuit Design :: 11-06-2014 18:28 :: SunnySkyguy :: Replies: **18** :: Views: **2371**

A Sallen-Key filter with **equal** resistor and capacitor values will have a Butterworth response when its **gain** is 1.586 and will oscillate when its **gain** is about 2.0 and higher. Try it with a **gain** of 1.8 times.

Analog Circuit Design :: 11-01-2014 14:57 :: Audioguru :: Replies: **5** :: Views: **1567**

The folded cascode has a higher **gain** than that of simple amplifier, but its **gain** is little lower than that of cascode. As far as I remember, the main idea of the folded cascode is that the input and the output common mode points are **equal**. Why do we need such a thing? in case you are designing multiple stages (cascading) in order to increase (...)

Analog Circuit Design :: 09-05-2014 17:44 :: Engineer4ever :: Replies: **1** :: Views: **520**

Hi,
I am finding Current **gain** of Common gate amp with gate biased and applying supply at source.
If I measure Iout/Iin getting 1 as current **gain** till mosfet is ON and when mos enters to cut off it is giving **gain** of sudden spike around 20.
and also by varying input sweep in steps 0.01/0.001/0.0001.
In this case source current is (...)

Elementary Electronic Questions :: 09-01-2014 09:05 :: raj_007 :: Replies: **1** :: Views: **550**

It's related to the fact that the **gain** of an inverting op amp is ideally **equal** to the Feedback-Impedance divided by the Input-Impedance.
As the frequency increases the impedance of C1 goes down. Since a reduction of the input impedance increases the **gain** of the op amp, the input RC causes the **gain** to increase with (...)

Analog Circuit Design :: 07-14-2014 05:56 :: crutschow :: Replies: **4** :: Views: **1077**

If the current **gain** is not **equal**, a differential output voltage will exist for an **equal** input current.
This is even more important if only a single ended output is used and current mirrors are used with a different Vbe characteristic. Some more info here

Analog Circuit Design :: 06-18-2014 02:27 :: SunnySkyguy :: Replies: **2** :: Views: **665**

They don't have to be the same but it makes the math simpler.
Correct - however, does this justify the dimensioning with **equal** components?
I don`t think so - because this has severe disadvantages.
Selection of **equal** component values requires a fixed **gain** rater close to the stability limit (which is "3") and the fi

Analog Circuit Design :: 03-18-2014 08:36 :: LvW :: Replies: **7** :: Views: **936**

Things are very simple.
Whatever **gain** the RX and TX antennas have and whatever loss is between them, the received signal power level (at RX input) cannot be higher than transmit power level (at TX output).
In the best case (and ideal) they can be **equal**.

RF, Microwave, Antennas and Optics :: 02-18-2014 08:33 :: vfone :: Replies: **11** :: Views: **670**

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frequency fdfd | impedance match hfss | adc gain | oscilloscope monitor | decoupling placement | signalling | inconsistent | logic analyzer problem | ecg analysis matlab | verilog writer