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21 Threads found on Error Amplifier Simulation
ENOB will always drop as frequency rises. You will have issues with the front end S/H amplifier tracking a faster-slewing signal. You could quantify the error at the hold node / A-D comparator front end.
Hi, I am simulating an amplifier in EM mode of Ansoft by importing the S2P file as an N-port model. Using the circuit designer with ideal loads of 50 ohms, I get the right gain (S21 parameter) of 13 dB. When using microstrip lines with physical dimensions corresponding to 50 ohm load, it shows -3 dB gain. I don't understand what I am doing wr
A simple differential one-stage amp with constant current source and diode connection load should do. No stability problem. Do u mean replacing the op-amp (the error amplifier) with the differential one stage amp?? Because i read about some CMFB architectures (check the images for examples) 118988[/A
Hello, I have designed a buckboost LED driver and have only so far simulated it. (in LTspice) The schematic is attached. Also attached is a LTspice waveform from the simulation. It shows the COMP pin and LED current at startup. (COMP pin is output of error amplifier) When I calculated the feedback loop with a certain method, it gave a (...)
Hello, In the attached schematic (and LTspice simulation) of a buckboost converter, the LED current sense resistor voltage is multiplied by 10 by the Current monitor (LTC6101). Should this factor of 10 appear in the small signal error amplifier transfer function for the purposes of plotting out the Bode plots and assessing the gain and (...)
Usually a DC feedback is applied in simulation to put the circuit into the intended bias point. For circuits with moderate gain, it may be sufficient to vary the input DC voltage manually until the bias point is reached. The circuit skips the LT1243 error amplifier and feeds the OP output directly to the comparator section. That's (...)
Hello, I am Designing a Power amplifier, The transistor selected is a freescale transistor (MRF6V2300N), luckily I have found its ADS design model, i have included it according to a tutorial, but while simulating it is giving following error.... Kindly guide how to correct this error?? any help is appreciated!! Thanks. [SIZE
Hello, We have done a simulation of a 15W flyback PFC in BCM using LT3799. (vout = 40V) The LT3799 is supposed to feature primary side regulation, however, we have added a secondary side error amplifier, and an opto in order that the secondary side voltage can be regulated to 40V. (as in the attached diagram) Is this OK? Can the (...)
The power supply rejection ratio PSRR of an LDO regulator essentially is given by the pass-transistor's power supply distortion feed-through, divided by the loop gain of the error amplifier. For a relatively large pass-transistor, the post-layout parasitics shouldn't change the distortion feed-through a lot; a gain reduction, howev
Hi there. This is my first post. How do i simulate the loop gain of a VR Simulator with Vref of 1.8V and power supply of 5V? Btw iam trying to recreate a wideband error amplifier.
I was simulating a differential amplifier with source degeneration.59268. I extract parasitics of M4,and add it in the circuit then do the post simulation. The current of M5 is 10uA. The current of M4 is 80uA during the presimulation, but the current of M4 is 592uA nearly the 8 times of the presimulation during the post simu
Hi All, I am doing DC simulation in spectre for my amplifier.But I get this error,in spectre.out Internal error found in spectre. Please run 'getSpectreFiles' etc... error detected in file 'ipsm.c' at line 219 Assertion failed. Has anyone seen this issue?Please help. Thanks and Regards Debasish
This is not a realistiv value so we should assume that it is a software error or you have a problem with your setup. It looks like you know what you are doing but I have to ask: did you place all the DC blocks at the input and RF blocks at the bias?
Hi, I have a question about the error amplifier in a voltage mode controlled buck converter. I designed a TYPE III erroramp with the correct transfer function to give me a stable loop in combination with the LC plant and the PWM modulator. According to the books, so to say. In simulation everything works fine, exept (...)
Hello all, i tried to co-simulate the amplifier attached but i have encountred an error which is also atteched. Is someone knows how can i resolve this problem, Thank you in davance, N
Hi, I designed TYPE-3 error amplifier. How can I ac-simulate my error amp? At first, I used macro opamp model(with 80dB DC gain, 10kHz 1pole system) and ac-simulated. My problem is when input common mode voltage varys, vout(s)/vin(s) are different! For example, in+ = 0V in - = 0V vout(s)/vin(s) is same as what i desired. (...)
Simulate the supply ramping with a transient simulation. Use either a positive and a negative offset on your error amplifier. If only one polarity works you get the issue. Startup in CMOS bandgap set the operating point at a value where the PTAT generate enough voltage to overcome offsets.
I would suspect some error in your schematic or component values. Another possibility is shortcomings in your simulation models. SPICE has very poor JFET models is an example. I have simulated a source follower that produced gains of 0.99 into the x-ray frequency range.
I believe that one of the the most critical questions, is how accurate is multisim compared to OrCAD in terms of simulation. For example i have created a simple bipolar amplifier and set the power supply to a very high value (40.000V). Even in this exotic case, multisim simulates the circuit - with no error message - and produces an output (...)
Hi People, I'm running a simulation for a optical circuit design which consist of a Limiting amplifier and a common mode feedback circuit. I'm facing a problem in cadence simulation, that is while running transient simulation it is giving the convergence error as in the attachment. This (...)