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8 Threads found on edaboard.com: Estimate Output Load

SMPS power supply +sense and -sense

Determine the load wire resistance and estimate the voltage drop. Consider if the uncompensated drop can be tolerated, possibly adjust the SMPS output voltage to increase the voltage to achieve 5V at the load under normal conditions. 5V/30A without separate sense wires is quite usual.

Output buffer for Sigma Delta Modulator

Any estimate of how much the rise/fall times of the buffer o/p signal (of 1MHz freq) at the pad should be sufficient? Usually (10*f)-1 should be sufficient, i.e. 100ns for f=10MHz .

zin and zout for an rf amp'

104149 hi all, thanks for reading. i want to ask if somone can please actually measure the input and output impedances of this amp' in above link (no spice models please). it would be used at 28mhz & power in on 20mw. for the entirely professional approach this obviously needs a Large Signal Vector Analyser. its a

Synopsys Design Compiler not responding to set_load

If you do not define any set_output_delay, there is no timing constraint on your outputs. set_load is "required" to estimate the delay added by the last wire to check if the setup is respected versus the set_output_delay.

Better formula to estimate energy output from a battery

I find most people using the following formula to estimate energy outputs from a battery for a given load: Assume a 12 V, 50 Ah battery (deep discharge type) Assume a load of 100 Watts, so using power formula P = VIcosΦ Or I = P/V I = 100/12 = 8.33 A Now, h = Ah/A = 50/8.33 = 6 hours

PMOS sleep transistor driving capacitance

Dear all, here is the scenario: I use PMOS header sleep transistors and I want to estimate the time required to drive the load capacitance. Basically, I am interested in the case when the control signal on the Gate is logical 0, the input (acting as a Source) is Vdd and the output (with the load capacitance) goes from 0V (...)

How to estimate the Antenna?s mismatch effect on PA?

How to estimate the Antenna?s mismatch effect on PA? performance(maximum output power and efficiency) and how to calculate the Antenna?s VSWR.

Problem with using NMOS source follower to drive pass device

Interesting. In both cases you would have a pole from the OTA driving the gate, and also a pole from the output cap and load resistance. In the common-source configuration your OTA pole could have miller effect which may have split across your output pole. Where are the poles now? Could you estimate each of the intended (...)