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35 Threads found on edaboard.com: Eye Jitter
For high speed signals an eye pattern can provide a lot of information. The data eye diagram is constructed from a digital waveform by folding the parts of the waveform corresponding to each individual bit into a single graph with signal amplitude on the vertical axis and time on horizontal axis. One of the properties measured using eye (...)
hi ,everyone I am using IC610 and MMSIM13.1. I want to observe jitter of a PLL output. And I used eye diagram assistant in VIVA to process the PLL output .But I got two totally different eye diagram.one is obtained by edge triggered and the other jitter is small .But the other is large I have already read VIVA's user (...)
Dear All, I am designing a conventional relaxation oscillator. The moninal frequency is around 2.85 MHz. When I try to run the transient noise simulation and use calculator to obtain the eye diagram, I got some weird diagram and i am very much confused. Attached you can see some waveforms obtained using the function eye diagram. The se
98292 Hi everyone I'm simulating DLL at the moment I want to see the jitter of my DLL. The top image is the specification of my subject. Then, how should I set my eye diagram range to check the jitter? (I'm using Cadence Virtuoso simulation tool calculator) Please Help me! T.T
Increasing frequency decreases the eye open time, but you need to know the transition time and signal jitter to do any useful analysis; BER is the statistics of how often an extreme jitter event violates the useful eye (period - risetime - falltime).
Hi, I am trying to implement an AND/NAND gate using current mode logic, and seem to have some trouble getting the output to exhibit low jitter. From looking at the transient waveform, there does not appear to be any glaring issues, but upon inspecting the eye diagram, it can easily be seen that the signal is quite poor. I have ensured that all tr
how to simulate the osc jitter in hspice (eye diagram, what to do)? and how to measure the jitter using Oscilloscope? besides, if the reference voltage of osc has a poor psrr, then can the osc jitter be larger? that is, is there some relationship between the reference voltage and jitter? thanks.
1) use PLL clock or clock /N to trigger data on scope for eye pattern 2) compare tx clock to rx clock jitter.
Hi all, I really do not know where to post this topic, because it is a bit related to digital communication I decided to post here. My question is slightly related to the theory and practice a bit. I have a DSP processor and designed PCB board, where this DSP soldered. Now I'm trying to check the USB port and have a bit problem with eye pattern a
Hi, i'm trying to plot the eye diagram of a jitter affected data using cadence spectre. In the calculator while using the eyediagram option, start time, stop time, period etc are asked. If my data has bit rate of 2.5Gbps and am running simulation for 100ns, what should be the above mentioned values set?. The plot is varying for different per
Hi, My simulation tool is spectre of Cadence. I try to obtain the data jitter from the eye diagram. The calculator has eyediagram function, in which there is a function 'horitontal opening.' The function can work very well when you do normal simulation, and it will return the value of your horizontal eye opening. (...)
Hello everyone, I have a question about simulation jitter in ADS. for the first step, I dont use to eye diagram, I only want to simulation the output signal of a ring oscillator with/without noise on its power supply, and compare it with measurement. From measurement, I got a statistal information about the period jitter, for example,
Hi As you might know, CEI-6G-LR standard does NOT specifically specify Rx input eye mask but it only defines 1200mVpp maximum. Maybe I'm missing something but how do you define CEI-6G-LR input eye mask for your design? Is there any jitter tolerance spec defined in it? Thx
Hi everyone, I the width of rising(or falling) edge in eye diagram is equal to the peak to peak value of jitter. But what type of jitter it represent for? long term jitter or period jitter?
Hi, I've designed CRC(clock recovery circuit), and want to measure the jitter characteristics using Hspice. I'm not familiar with HSPICE, jitter, eye diagram, etc. Here are my questions. 1. I'm using PRBS patterns for the input data. Are they right to be used in my case? 2. I'm using Custom Waveview for the simulation of my (...)
Hi, Ok, I simulated my LVDS receiver using input K28.5 pattern at 1Gbps. The eye diagram shown below is the eye pattern at the output. My question is, why is it that the waveforms that constitutes the eye are grouped into separate strands? The data pattern i used is K28.5 or 0011111010110000010... --andrew
hi, i wanted to generate eye diagram for USB FullSpeed Driver to measure jitter.Would any one suggest me,the PRBS pattern,need to use for generating eye digram? pattern means how may bits..bit time etc... Thanks
In sandwork, we easily measure prbs pattern jitter with eye diagram. However, can we measure the eye opening and jitter in cosmos-scope?
Hello friends.. I need to find the jitter from the eye diagram for LVDS for all corners. So how to calculate the jitter from the eye diagram in ocean script.. Please help me... Thanks in advance shady205
Hi All, I am not well acquainted with ocean scripting. Could any body tell me how i can write the command to measure " the jitter from eye diagram " using the ocean command. Thanks.