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311 Threads found on edaboard.com: Feasible
ANY fpga will do this. Basically yes. In detail, your design complexity and FPGA size decide about the feasible parallel inverter controller instances. Matlab/Simulink communication capability depends on the intended interface physic, e.g. serial, ethernet, whatsoever, required data throughput and latency. What do you want to ach
The primary use of digital pots is for circuits that need a variable resistor or a true potentiometer which doesn't work with R-2R ladder. The resolution is respectively limited by the feasible number of analog switches.
Most resistor values are off feasible resistance range, the circuit can't work with the given dimensioning. You need particularly to consider available output current of LM124 and LMC3702. Also the input offset network is apparently not correctly calculated (besides too low resistance values). - - - Updated - - -[/
FPGA internal RAM can access one or maximal two (by using dual port RAM) locations per clock cycle. In so far it's not feasible to perform the intended comparison with 1000 RAM locations in 5 or 10 clock cycles. Distributed RAM can work faster, but as it's implemented in logic elements, it involves a large amount of FPGA resources. Another opt
with these code, the number increments by 3 secs In preemptive operational systems ( which it is supposed to be your case ) it is not possible to accurately generate tic time at short intervals. The only feasible option is to use the Interrupt (IRQ) feature for this. In the past I have done this by external interruption with a cry
Anyone have any experience with RFID tag designs which rely on transmission lines and captive gaps to "encode" a reflected signal Doesn't sound to me like a feasible concept. Which RFID frequency band do you target at? Required transmission line length would be commanded by transmitter and receiver bandwidth respectively system tim
You probably request a "non feasible/tight" response from this filter.I mean extremely high attenuation in ban-dstop region, very narrow-band etc. characteristic. Therefore the filter elements are uncommon for 400MHz.I suggest you to loosen the specs. of the filter in order to find more realizable components.
300 kS/s is the minimal sampling rate according to Nyquist theorem. Practically, there must be a margin between the highest signal frequency and fs/2 to allow feasible anti-alias filters. 330 to 350 kS/s is more realistic. Regarding VS1053, just review the datasheet. It's maximum sampling rate is 48 kS/s. Maximum sampling rate of high performanc
It is feasible to drop 3V with a transistor or IC regulator. However you waste 15W at 5A. To have efficiency you're probably looking at a buck converter. Although your output spec is 4A or 5A max, the inductor may have waveforms with peaks upwards of 6-8A going through it. It gets complicated when you want to regulate output voltage, and at the s
Absolutely agree with the above, the thing is almost impossible. However, in this particular case, perhaps there is hope: Use the Proteus 'Swiss pocket knife', the EasyHDL scripting, with which almost every feasible. Search for it on the net. The Proteus EasyHDL uses a basic-like programming language, the existing C++ source only (:win
To find out if a circuit can be layed-out on two layers, I would define the PCB form factor and placement constraints and then check if it's feasible. There are many points why four layer can improve the design compactness and EMC properties. However, if the GSM and Wifi modules contain all necessary filtering and only require power, data and an
The FET switch signal range is limited with respect to the feasible gate voltage range, as you said avoid inadvertent turn on. FET maximum rating might be a problem too, depending on the OP supply range. - - - Updated - - - Why do I need a resistor R4? Guess you don't necessarily need it.
Without going into the design details (AES encryption details)... What can be done is already mentioned in simple English #1 to #3. If you cannot use a larger device (#1) then go to #3. I am assuming you have specified the correct no. of top-level ports (#2), else re-check. If #1 is not feasible then #3 is your only option. Reduce the encr
Only a theory: Most likely as your input voltage increases, the flyback starts operating in DCM. If the SR controller keeps the gate energized in this condition, it is feasible that some current drains away from the reservoir capacitor. To validate the theory, you really require to probe with an oscilloscope. The primary side probe
According to sampling theorem, the sampling rate must be greater than twice the highest frequency component in oder to be able to reconstruct the original signal from its samples. Higher sampling frequency is feasible. This facilitates the reconstruction, The only disadvantage is an increase in the storage requirements or transmission rate
You'll use a combination of analog and digital filtering. Have a feasible bandpass, e.g. +/-2 to +/- 5 MHz stop band, band pass sampling with sufficient rate according to the Nyquist criterion, digital filters for the final receiver characteristic. Alternatively sampling with high rate and purely digital filtering. Preferred implementation accor
Hi, In an opamp, we can set the input-pair MOSFETs to be in Sub-threshold region of operation. To what extent can we put them in sub-threshold?...like, can we use (Vgs - Vth) negative? As I searched in forum posts, people say they use (Vgs - Vth) ~ 100-200mV which makes the MOSFET near subthreshold..but is it feasible to use a Vgs so
Have you tested your motor to see if current draw goes up when stalled? It is common for a stalled motor to draw increased current, and perhaps to burn a winding. Therefore it might be feasible to design your control circuit so it detects a jump in current. That tells you when the door has reached end of travel. Then your circuit should immediatel
The parameter OPT presupposes the existence of previously calculated values, so that honestly I can't see how to dynamically set values to insert them in simulation as initial conditions without those being already known. In other words, the only thing that seems feasible is to store these bias points once at a certain number of simulations and the
Hi, I have found this simple SSB excitter on the net. I would not expect a great opposite sideband or carrier suppression, but do you think this simple scheme that uses the phasing technique for ssb generation, is feasible? I have no idea about the input and output transfirmers of the modulator. I guess the output transformer should be trifilar. A


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