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31 Threads found on Fet Drive Circuit
The MOSfet with G=S=B=gnd! will change behavior if you try to drive the drain negative. Presuming the body diodes are well modeled, you will light up the D-B diode when you go much below ground. When you try to impose more current than the fet channel "wants", it has to go elsewhere (like into your shunt resistor). If you probe the (...)
I am testing this gate drive pulse transformer circuit but the top 2n2222 connected to positive rail runs hot the ground one runs cool should they not have used higher current transistors to drive s coil?. and should there not be a 1k resistor on its base as well as the other if anyone can help?. 131870
I think this option has more potential if you reduce the coupling capacitors and apply more damping. - - - Updated - - - Measurements on a breadboard test circuit also look promising. Trace one is the primary drive signal and lower trace measured on the gate of main fet.
it looks ok but those bootstrap circuits can be bad if the fet vds transitions at more than 50v/ns....gate drive txfmr is better
It's almost a certainty that your turn off losses will be excessive without the solid low-Z turn off provided by pnp xtors Many have tried to design simple xfmr gate drive for high power levels, almost all have failed - pnp's etc are so cheap - why not ensure decent product life? - - - Updated - - - p.s.
121873 Hi guys, I build this circuit out of curiosity to make DC to AC converter for my workbench (sorry 'bout the drawing in it). Try to configure this i use 555 timer to generate 120hz to make the flipflop generate 60hz then I added 10k, 1k resistor and a 1uF resistor then i use a d flipflop as my inverted output at
Depends on how fast you want to switch the fet. Gate rise and fall times will suffer from Z-diode capacitance and relative high driver circuit impedance. An active pulse forming circuit, e.g. a CMOS gate or dedicated gate driver at the high side potential would be preferred. Average current consumption is (...)
You could even use the PV sensor to drive an NPN to disable a self biased Type N fet to switch the LED from the low side.
Hi, looking for help on my gate driver + fet circuit. The issue is that the node between the fets of the half-bridge drops to about -8V relative to the GND of my gate driver when the top fet turns off. I believe that this is largely due to the parasitic inductance of the (...)
Hi unipolar motors are easy to drive the center taps of the coils go to the supply voltage. the coils can then be pulled to GND using a fet. you will need 4 fet's in total one for each coil. Don't for get to add diodes across the cols to help with back EMF from the switching. If you need more help let me know.
I don't see an initial drive on the fet gates?
You don't know, a priori, what "corner" affects a circuit's numerous performance dimensions. There are often competing interests such as drive vs leakage (and that's just one fet). This is why Monte Carlo is more interesting, even though it's a slow-motion pain in the nether sphincter.
Hi, When driving a switching N mosfet with GS capacitance "C". The energy to switch the fet on is 1/2CV^2, where V = 10V say. Therefore the power consumed by the gate drive circuit is 1/2CV^2.f This equals why does the equation at the top right of page 8 of the following call it (Qg).V.f ?? ..Surely they have m
You're not going to get those kinds of speeds from an IGBT and likely not a MOSfet either. Maybe you should think about doing your modulation at small signal rather than at high power.
FVM is right, you have your circuit backwards. The drive to the fet should be your digital signal. The fet will short out the sine wave when it is ON, and will pass the sine wave when the fet is OFF. Also, to actually send data on the sine wave carrier, the sine wave frequency has to be much higher than (...)
Hi, In the attached figure, you can see that a P-fet (Power MOSfet) is to drive a big solenoid which operates at 8A constant current. A current sensing circuit and one or two filters on the line. one MOSfet driver is driving the P-fet (not shown in figure) at certain (...)
Simplest solution could be to use a N type fet with its drain pulled up(with the help of resistor) to VCC and source to ground. You can drive it gate with FG and get the output from drain. In this circuit your output will be inverted. Umesh
The switching speed of the fet is slow and so there is an extended period where there is voltage across it while current flows through it. This is probably caused by the limited drive current sent to the capacitive gate-source part of the fet. I would suggest that you use and IC specifically designed to drive (...)
if I use a p-channel the Vgs voltage will be exceeded by the Voc of 22VThis seems to be a problem of the simple circuit you imagine rather than of the P-fet as such. There are always means to drive a suitable voltage to a MOSfet, independant of the converter toplogy.
Two comments: - You can't drive a NMOS-fet this way. It needs 5 to 10 V Vgs to turn it on. Switchers with NMOS output stage typically use a bootstrap circuit to drive the fet. Consult existing circuit examples. - A buck converter with unregulated PWM gives very poor output voltage (...)