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57 Threads found on edaboard.com: Fifo Vhdl
fifos usually have control signals: Write side: full and enable Read side: empty and enable With these 4 signals, you can tell if there is a word in the fifo and enable the next one on/out of the fifo.
Hi, I wrote these Components. I simulated both of them and they worked correctly but in implementation(Spartan-3 50MHz), they sometimes work and sometimes don't. 1- Debouncer: There are two counters : Clock_Divider_Counter (Works with 50MHz) and Debounce_Counter (Works with 1KHz) If Bounced_Start (Input) is '1' for about 100
I opened a project and tried to make a general fifo using "fifo generator". Target language is set to Verilog. When it is done, but I received a vhdl type of source code instead of Verilog. In same project, I took a Clock Wizard and can get Verilog type of an MCMM. Does anyone meet the same issue ? Is that the exception for (...)
Can someone advice me an already written Asynchronous fifo (2 Clock fifo) code in vhdl, possibly already used without problems? All the codes I've found generate me some errors. My FPGA manufacturer fifo's when I try to read and write at the same time it create me problems in simulation and also I can't modify it or adapt (...)
I don't believe that using SV or plain Verilog (or e.g. vhdl) makes a big difference when describing the basic operation of your bitwise fifo. You need to describe it in a way that can be mapped to hardware. It's helpful to have an idea of the possible internal structure, e.g. using BRAM or registers only, using a combination of a 32x32 (...)
Hi, I want to create a circular fifo to reuse the free memory. Here is my code: library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity ring_fifo is generic( fifo_length : integer:=8; data_width : integer:=4); port( clk : in std_logic; rst : in std_logic; ren : in std_logic; wen : i
Hi, I have a vhdl code, and there is a fifo ip core in the code. I have copied the .vhd files and .ucf files and also a .v file and ipcore_dir directory to another directory and I tried to synthes
I think its having reset problem; first u check your fifo reset it '0' or '1'; and it sync or async reset, and your global reset is asyn means given fifo reset after 100 clk cycle delay;
Hello, Please, I need help about how could I use fifo in my custom IP core? I want to store many data in write fifo and read fifo, but how could i store data in write fifo ( in user_logic.vhdl) If there are any tutorial explain how to store many data in fifo in vhdl (...)
Hi Well done on this, but why would anyone chose your async fifo over the ones created by altera and xilinx that you can use for free already? And it doesnt inspire me with confidence when you have conflicting libraries in your async_fifo.vhd and testbench files.
hello, i need a vhdl code for fifo memory to store binary values from a high speed 8 bit resolution adc. can help me give the code and the ucf file for implementing it on spartan 6 sp605( fpga kit).?? thank you you can automatically generate it with xilinx core generator (coregen) you can find it under :
Dear all, This is kind of urgent but in no way at all DOING-HOME-WORK-BY-SOMEONE-ELSE kind of thing. I am just stuck with time and have less experience of simulation over vhdl I usually use verilog for my simulation but this time I have to use vhdl (dont ask why...obsessed with timing :cry: ) Any how the thing is I have to read the entire fi
Hi all! I am trying to interface a fifo customized peripheral to MicroBlaze in Verilog because I do not know vhdl. I have got through the stuff available and tried some of them too on my Spartan3e 500 kit. but i am unable to acquire good results. any guidance for me?? Thanks in advance! Luqman
Not vhdl but good anyway:
Hello Friends, Kindly, I am writing a code for fifo - RAM to use it with my UART controller. Now I got the code for the first part which is the fifo + RAM. In fact it is not my code, I found it on the net which is as follows: library IEEE; library work; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; use work.all; ent
Hi friends, I am designing a fifo handler but I face an error message in the If statement. Part of my code is: library ieee; use ieee.std_logic_1164.all; -- fifo Handler Entity fifo_Handler IS Port(Rx_Ready : in std_logic; Data : in std_logic_vector(7 downto 0); Tx_Req : out std_logic; Rd_Req : out std_logic; F
Hallo all, I am writing interputs for a fpga and dsp need to interact with a dual port memory shared dpram control in vhdl. I have External IOs coming from the SPI bus on oneside to the fpag to be communicated with dsp and on the otherhand have a camera to the to the dsp. So my intrups are like Havinf a fifo being reset after everytime a FSM r
Hi there everyone, im studying FPGA programming independently and currently working my way through Dr Pong Chu's book RTL Hardware design using vhdl. Im a programner by day coding in PHP so while its a bit of a paradigm shift for me, its an enjoyable challange. I'm currently on the chapter 12 RT methodology - practice and attempting the exercise
Hello, i'm new here and new to the altera morphic-ii. I have problems to get the usb connection between the host pc and the cyclone fpga to work. I want to use the ft245 mode of the ft2232h. On the pc side, i use the vcp driver and have programmed the eeprom with the ftdi tool. Both cannels in ft245 fifo mode. After this step, i have programmed
Hi, Any one have any refernce document or code for design the ping-pong fifo in vhdl or verilog. Thanks and Regards, Kanimozhi.M