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It's the speed at which you fail the first of many ADC accuracy specs. I recommend you look at the definition of ENOB, implement the tests that show the elements of it, call your goal 3.5 bit accuracy at speed (as 4.0 would be a fantasy) and grind out the characterization.
Generally speaking why would someone want to write a test-bench that will go into implementation (asic/FPGA doesn't matter)? I would question that design in the first place. I have tested my DUT in simulation using VHDL test bench. The test bench has behavioral coding. I want to use the same test bench for validation on FPGA. So the tes
first of all this should have been posted in the asic Design Methodologies and Tools (Digital) forum. Start with the ARM AHB spec first and understand it. A two master and two slave scenario is relatively simple. You must 1st understand how an arbiter (the arbiter decides which master has control of the slaves) and address decoder (th
design and verification are quite orthogonal, and one would usually focus on only one. for design, I would first learn verilog and synthesis. You can go about using tutorials, books might not be the best source. for verification, I think Bergeron is a good author. OK, what's the difference between design and v
first of all you have posted this in the wrong forum. Post this in the asic or FPGA forum. What about all the other signals (for example ARBURST,ARLOCK,ARCACHE,ARPROT,ARQOS,ARREGION)? There are many more signal according the specification of AXI4. Just going by a glance, there are many signals which are optional so they might be mi
I read many times that the first years of work are really important to set the future career path This is true in regard to establishing your work history as a reliable and competent employee. You want to receive good references, wherever you are. Career paths change. It is very common for people to move
I would suggest to have the following constraint first. 1. clock period 2. input delay 3. output delay 4. clock uncertainity 5. clock latency 6. set load 7. set input transition 8. False Path / Multi-Cycle Path ( between the clock domains if any ).
This sort of reads like a technical marketing blurb at least the first couple of is a 4 wire interface that is pretty much ubiquitous on every processor, ic, asic, fpga, cpld, almost any complex digital logic ic in existen
This should not be your first FPGA projects. They are too difficult. If you really want to go ahead, start with the decompression since it is much easier, but still difficult. MJPEG (Motion JPEG) is easier than the other compression methods since there is no interframe prediction. Each frame is just compressed separately using JPEG.
how to use test bench To understand how to use one you should first know what they after you know what they are, you need to learn how to write them...
Hello, Decide first on your Op-Amp application. That will help.
Did you even try googling "Verilog forever loop"? The first link returned was: has the following code: initial begin #1 clk = 0; forever begin #5 clk = ~clk; end end You should also add a `times
This should get you started: The first link is for verilog, but the concepts are oooh lets say, exactly the same. And since your question is largely "How testbench wrk?" the basics covered there should help. PS: Just out of c
Hi Rakesh, The following books are useful for PD first read the book thoroughly, you will get good knowledge on PD Follow the blogs All the best
This is the first Verilog code I wrote. It compiled successfully in Questasim 10.1b. I want to know how to Use the simulator to simulate the project. // 2-input OR gate `timescale 1ns / 1ps module OR2gate(A, B, F); input A; input B; output F; reg F; always @ (A or B) begin F <= A
Dear Engineers. If anyone worked on power optimization using DC compiler from synopsys I have some questions and hopefully someone can help. first of all is there any tutorial for this design tool?
Some thought it means the delay from the signal source to the first register in the core design. But according to <asic timing verification> book, it seems that it means the delay from the signal source to the first stage circuit (no matter register or gate) in the core design. These two explanations are totally different. And which is right?
first: The constraint concept is the same. Such as you need constraint clock period, identify false path, identify multi-cycle path, define input/output delay. While each tool has different timing constraint syntax.
Hi everyone, I an new here and this is my first post. I am a newbie to asic and as part of my semester project I am implementing a 3TDRAM. I am using 0.13um technology and Cadence Hspice and Spectre tools. I am running into some simulator issues. 1. I initially started in hspice but realised I had to do monte Carlo so i switched to Spectre. But w
To answer your question, first important thing we have to know is what's your target device. Is it a FPGA or asic? Ans to Q1 :- If its FPGA then in data sheet you will get the FF delay before hand. If its asic then foundry will share this data with you. Ans to Q2 :- It all depend upon you design. You have to have a understanding of you (...)