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53 Threads found on edaboard.com: Fix Setup Hold Violations
When simulating without SDF (path delay mode) you can get timing violations if your design contains clock with some logic (adding delays) on it. In this case you need SDF simulation. When using SDF with pre-layout netlist, you need to fix hold (and of course setup) violations before simulation to avoid (...)
The main intention for checking hold time is to make sure that the previous data is not over written. So if min path data arrives to fast just after the clock then u will get hold timing violations. u have to fix these by adding delay buffers, so that ur min path is delayed. Hope it clears ur doubt.
fix the setup violation, then buffer the hold violation at the Q pin of the launching flop with the hold violation (or at least somewhere on the path not common to the setup violation) This is assuming the violations are not from the same launching flops.
HI, hold violation can be fixed by adding a delay buffer at the Flop, provided the setup violation dont occur at that flop. So adding a buffer, should be done considering the setupmargin. So my question is if the setupmargin doesnt match with the hold in different (...)
What is the reason behind fixing the hold violations after the CTS?
Functional ECO - to CORRECT/Change the design functionality after the implementation has started and dont have a chance to go back to synthesis Timing ECO - to fix all timing violations such as setup, hold, recovery, removal, DRV (max_fanout, max_capacitance, max_tranisiton)
Hi, fixing setup violation of a path to a margin (Say just getting a +ve slack) cannot result in hold violation. But the same endpoint may have many paths with different start points which can have hold violation as the result. Hence fixing setup violations should target (...)
Hi, can any one let me know how do we fix setup and hold after CTS. I am not having any setup and hold violations before applying derates, but after CTS when I apply derates I am facing lott of setup and hold paths which are violated.Can anyone help me out (...)
Thanks randyest. Its like taking the advantate and setup and hold interdependency to fix the hold violations right, by having negative hold time at flop
hi all i have setup and hold met with good margin of postive slave, but i have max trans and cap violations, still i need to fix them? if so why we need to fix them even after meeting setup and hold with good margin Thanks in advance
One more reason of fixing max transition violation is that bigger transition will result in bigger DC power consumption
Hi, I am new to Timing in Physical Design and I would like to know Why do we fix hold violations in the Min Corners{taking delay values from min corner of .lib's} and setup violations is fixed in Max Corner {ie reports & libs are used from Max Corner}. Please clarify on this... Thanks...
Hi all, In Astro we get max transistion and capacitance violations if any in the timing report itself and also options such as gate sizing and buffering can be enabled for fixing it. In Magma hw do we find out these violations. the timing report gives only the setup and hold values and wat r the (...)
its better to fix the setup violations b4 the P&R of the design , cos u have to ensure the ur design meets the specified/expected freq !! only the hold viol ( minor violaions) can be fixed after the P&R ! WBR Lakshman
For fixing hold violation between two registers, various techniques are there, 1. try to add delays cells in between the registers without violation setup timing 2. try to utlize usefull skew in the clock paths betwwen two registers. etc.. for fixing setup, 1. try to optimize data path between two (...)
When i run FPGA, I found some hold time violation. how can fix them? Thanks! David
PT, as far as i know, can't fix the timing violations. but, hold violations are fixed using buffers in the P&R stage, or by adding an additional flop(making sure functionality is met) in the RTL stage. For setup violation, either better constraints or methods such as inserting buffers in (...)
it depends on how u fix setup violations 1. can be register balacing 2. reducing combo logic 3. by clock skewing. setup fix may lead to hold violations . for example to reduce setup the hold window will get reduced if combo logic is (...)
how to fix setup and hold violations using pt and without affection eachother means setup should not affect the hold and hold fixing should not affect seup
Hi phutanesv, You are right hold fixing before tapeout is must. If you do not fix the hold your circuit will not work at all (hold requirement does not depend upon frequency). If your have setup fails then still you can work at lower frequency. So the flow is 1. (...)