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53 Threads found on edaboard.com: Fix Setup Hold Violations
Hi leeguoxian, This is a common problem in multi scenario design, but could you explain me why 2. First , I fix all timing violations in function mode. Then I use astSetDontTouch to all cells. And then I turn to Scan mode and fix hold time violations. Doesn't Worked. does not worked. I assume (...)
Hi, How to fix Timing violations(setup & hold time violations)? What are all the things that has to be taken care while fixing it? Hi , setup violation can be fix by insert registers in worst path. holdup violation can be (...)
as tarkyss, The fix for setup violations depends upon which stage of the design flow, the violation has occured. if it occured during P&R, it can done by rechaning the cell palcement, the cell resizing, clock path delay adjustment..........etc.... If the still the violation exists then u have go back to ur synthesis stage and (...)
Hi I will fix hold violation first.because it is easy to fix.And I think the setup violation is easy to fix on frontend but difficult to let the setup violation be there if the design is not small. Above all ,setup violation makes us to decrease the freq,but (...)
To fix set up violation, one thing is optimizing the combinational logic in the critical path.. if its not possible using pipelining concept thats...divide the combinational logic using a register in critcal path.if that is also not possible, then add buffer in the clock data path to 2nd register to meet the setup time.. To fix (...)
in pre-layout pls fix the setup times in synthesys. hold timings are fixed by back-end during post-layout phase. i agree with this. my suggests is using phycial synthsis to synthsis the design in DSM era, like PKS and PhyCompile, all of those have commands to fixed setup and (...)
If setup violates, design output will be wrong. But if hold violates, design may not function. MUST fix BOTH setup & hold setup - fix in pre-layout phase before CTS hold - fix in post-layout phase after CTS
Dear sir : using slow corner lib to synthesis your design in order to fix setup vio. or adjust your code . or if you have latch or ff in your design shift it forward until you fix setup vio. (but sometimes this is done by tools ) then fix hold vio in backend because ... people (...)
If I must do the choice, I will do the latter , because the latter can be fixed by adding some combinational logics so easily
Transition fixing Question: What commands are available to fix maximum transition violations in Astro? Answer: The following are some commands that can be used to fix maximum transition violations in Astro. Transition fixing can be concurrent with (...)
setup time violations are corrected in two ways. First, extra buffers can be inserted to speed up slow signals. Second, if buffer insertion does not completely fix the setup violation, the placement can be re-optimized. hold-time violations are fixed by inserting (...)
Hi , all: I put forward a new idea about how to fix hold timing violations, anyone intresting in this field pls give some points, thanks. OK,in normal case , we synthesis the RTL code in DC, in the synthesis envirnment , we don't care hold time violations. then we do place & route in (...)
1. setup and hold times are for flops not for design.. u need not calculate it. the fab will caluclate and u have to ensure that these timings are not violated in your fix setup/hold violations redesign your logic... try to reduce the combinational path delay , wire delay , parasitics (...)