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53 Threads found on Fix Setup Hold Violations
Hi, how to fix setup and hold on same path, if we fix hold increase setup violation, and if we fix setup increase hold violation.
Hello all , There are times, when I am not allowed to change the RTL, and all the clocking structure in the design are already optimized. Still I face situations where I have negative slack ( setup as well as hold ) Some times by trying few strategies in Vivado, the tool solves the timing violations, but what if it doesn't ? Question (...)
Hi All, If ur data path is optimized ( 2 flops and a combo logic) and have setup violation,what option you use to fix setup violation ? Could u answer this ?
Hi frinds.. after post Route fixing setup/hold still i'm seeing some transition violation and fanout violations how to fix them , what are the violations are real....? here are the Fanoutviolation info... ---------------------------------------- *info: there are 121 max fanout load (...)
Hi folks, I have seen few zero cycle ( set_multicycle_path 0) setup paths in design. Can you explain why there is a need of having 0 cycle setup path? what is a advantage of the same? How do we check hold violations for these kind of paths? These paths are violating setup time. How can (...)
Hi All Is there any special commands for fixing setup and hold violations after post Route. optDesign doesn't looks good and it couldn't optimize the design. so I think I have to use setOptMode to set some values.. But I dont know the exact parameters. Can anyone Please Help me? thanks
Typically, you don't worry about hold fixing during logic synthesis. You'd only try to fix hold violations in P&R after CTS. So yes.
check this link fixing setup & hold violations
Why do we fix set up violations in pre CTS stage and hold violations after CTS?
Well the tool will identify the buffers using function statement in the .libs. So any function A=Y will be considered as buffer. You can use eco_opt_design -hold to fix the hold times. I am assuming you will be adding parasitics and other other design rule constraints to EDI interface.
Hi all, in my design after CTS, i have 132 hold violations, and 100 setup violations. how do i can fix with help of ECO. i'm new to ECO. please help me to write ECO script for setup or hold. thank you..
So before looking to the setup/hold time report, you must have the trans/cap violations clean or so small than the impact is reduce. So rca - Lets consider PT - so all you are saying is first of all check for Max trans/cap, fix it, and then you check setup/hold and fix (...)
The basic questions will be on 1. Clock constraints (master clock, generated clock, clock skew, jitter, clock network delay, source delay) 2. Input and output constraints 3. Virtual clock and the use of it 4. False path and multi cycle path. How will you identify them. 5. How will you fix setup and hold violations 6. What is (...)
Used STA tool to do eco fixing, and it will report the cell needed to fix the timing issue. But the first question, are you able to fix the hold after CTS or/and after routing?
Hi All , I have internal and external violations in my design . By Internal I mean Reg to reg paths, By external I mean " Input pin to reg " and " reg to output pin " . How to I go about fixing them ?? Should I remove my internal and external setup violations first and then fix (...)
Simple during pre-cts no actual clock will be preset and hence no need for hold check. We will clear set-up violations, do CTS and fix hold violations if any occur.
Hi all , In one of the interview , I was asked : do we need to fix every clock transition violation " ? I replied yes.But it seems the answer is no . I was told to find out why ? Please help me by answering it Thank you jaya sree
during the synthesis phase you only fix the setup time. hold time is only done after clock tree in PnR tool.
Prime time can fix setup, hold and drc and write out a tcl script to run in icc.. ---------- Post added at 06:26 ---------- Previous post was at 06:24 ---------- Pls delete this post. It was submited by excident.
There are many other methods than sizing to fix setup violations. 1. Logic restructuring: Reduce combinational logic delay by minimising number of logic levels. 2. Vt swapping: Sweeping HVT by RVT or LVT. Standard cell library has three type of cells. HVT(High threshold voltage), RVT (Regular threshold (...)