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22 Threads found on Fixed Point Division
Some Microchip fixed point libraries do provide multiply and division. The question would be much clearer if you mention the processor family and exact library version respectively give a Micrcochip link to it.
hi .. in division that includes fraction , i am using fixed point the division includes negative numbers too..but i have a problem . For negative numbers i am using 2's complement methode and i dont know how to represent (-.5) using 2's complement. is it possible to represent numbres like -.25 (...)
Hi, I am trying to do a code for do division using verilog that is work with fpga. The thing is division operator is not syntyhesizable.I am using fixed point arithmetic to represent a number (includes fraction),think the only methode to do it is loop baised substraction methode or quotient remainder methodeIis there (...)
There's no need to change anything to fixed point package. It's just a kind of wrapper around integer arithmetic making your life comfortable. But you can do anything manually as well. As a first step, you need to figure out the right scaling, preferably using pencil and paper.
dear all, I need to do the division of two fixed point numbers.Can anybody help me to do coding for this. eg: 1.75 /1.5 1.75 is 0000000111000000(16 bit representation) 1.5 is 0000000110000000(16 bit representation). 1.75 /1.5=1.166667. =0000000100101011.
Google around for "verilog fixed point" and you'll find some inspiration...
fixed point is just integer arithmatic.
Hi all, Does anyone know of a division function in C for fixed-point numbers? I am using ac_fixed header but apparently that doesn't work since I'm getting zeros when I do 1/a where "a" is a fixed-type with values between 30-60. Thank you, Elnaz
Hello, I need to 1. convert integer to fixed point 2. Then perform functions such as division and exponential equation Do you know any library or function for this? I know about mega functions but that is for floating point and it will require alot of resources that will be needed for other computations in my (...)
i wanted to implement fixed point format division in verilog. can anyone help me?
hi all i need yours help for some little implementation algorithm in FPGA i am using uart that gives me 7 bytes of ascii codes , 6 bytes on integers and one byte of point in that way XXX.XXX i need to create a floating point vector - i mean to sub x"30" from each integer byte and collect the integers to floating point vector/ (...)
what problem are you getting? general refusal or timing failure? I would never use the "/" operator directly because it offers no pipelining. For a decent clock speed, you will need several pipelining stages, which is probably why you are getting failures. Altera and Xilinx ofer fixed point divider IP blocks.
Arithmetic functions (e.g. sqrt, division) are operating on numbers, not bits. These numbers have a digital representation. The first point, when thinking about lookup tables, is to specify numeric ranges and resolutions, then about a suitable numeric format, mostly fixed point. There's a large amount of contributions (...)
Hi, maybe this links helps ) High speed fixed point division in FPGAs ECE 645 Spring 2009 regards
Hi, I want to do floating point operations like multiplication, division and square root to calculate PWM duty ratio in dsPIC. I want to do these operations at high frequency. But I am encountering problems because my dsPIC is not able to do all the floating point computations at high frequency rate. I know that fixed (...)
So the value will always be between 0 and 1 and I require upto 3 decimal places. Binary arithmetic doesn't know decimal places. You have to choose a suitable representation for the result first. My suggestion would be a binary fixed point format with a factor of 2**10. It can be easily achieved by extending the numerator to 34 bit
Today's HDL synthesis tools don't support Verilog or VHDL floating point type, but you can use fixed-point techniques instead. For example, 0.02 is approximately equal to 1311/65536, so you could multiply by 1311, add 32768 (for rounding), and then right-shift by 16. For higher accuracy, use larger terms in the ratio.
Hello dear, I need algoritm/ guideline on fiexed point division in vhdl. Secodnly, how to check that in how many cycles FPGA performs an operation(i.e. +, -, / etc.).
hi everyone can anybody help me in writing a code in fpga for divsion division which is for signed number s n also for fixed floating point plz thanks
Hola namqn, I recall a FPU, probably that one, which had a fixed delay for reading its data of about 200 usec? Is it this one? Good to keep in mind, before buying.