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## Fixed Point Division |

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floating point fixed point , fixed point , fixed point multiplier , fixed point vhdl

22 Threads found on edaboard.com: **Fixed Point Division**

After spending the past few days getting the **fixed** **point** library to actually build, I was shocked to see that there are only Add and Subtract functions in the libq.h
First question is why no Multiply and Divide?
After playing around, I did get the the following code to multiply and give the correct result:
_Q15 a1 = _Q15ftoi(0.25)

Microcontrollers :: 10-28-2016 04:38 :: chinuhark :: Replies: **5** :: Views: **1570**

hi ..
in **division** that includes fraction , i am using **fixed** **point** the **division** includes negative numbers too..but i have a problem . For negative numbers i am using 2's complement methode and i dont know how to represent (-.5) using 2's complement.
is it possible to represent numbres like -.25 (...)

PLD, SPLD, GAL, CPLD, FPGA Design :: 08-05-2014 10:01 :: dipin :: Replies: **1** :: Views: **690**

Hi,
I am trying to do a code for do **division** using verilog that is work with fpga. The thing is **division** operator is not syntyhesizable.I am using **fixed** **point** arithmetic to represent a number (includes fraction),think the only methode to do it is loop baised substraction methode or quotient remainder methodeIis there (...)

PLD, SPLD, GAL, CPLD, FPGA Design :: 07-30-2014 11:44 :: dipin :: Replies: **20** :: Views: **8709**

Read a **fixed** **point** notation like A.B as N_integer_bits.N_fractional_bits.
As you are using regular integer **division**, you get quotient_fractional_bits = dividend_fractional_bits - divisor_fractional_bits. For > 0 fractional result bits, you can add bits to the right of the dividend.
Or use the IEEE **fixed** (...)

PLD, SPLD, GAL, CPLD, FPGA Design :: 04-01-2014 07:13 :: FvM :: Replies: **12** :: Views: **1509**

yes, the simplest VHDL is:
output <= input1 / input2;
using the numeric_std or **fixed** **point** library.
But this will only produce a maximum pipeline length of 1. To get better pipelining, you need to use a divider IP core, which is provided by both altera and xilinx.

PLD, SPLD, GAL, CPLD, FPGA Design :: 10-04-2012 08:09 :: TrickyDicky :: Replies: **12** :: Views: **8272**

Google around for "verilog **fixed** **point**" and you'll find some inspiration...

PLD, SPLD, GAL, CPLD, FPGA Design :: 10-14-2012 18:14 :: mrflibble :: Replies: **2** :: Views: **2957**

PLD, SPLD, GAL, CPLD, FPGA Design :: 03-22-2012 11:41 :: TrickyDicky :: Replies: **9** :: Views: **3919**

Hi all,
Does anyone know of a **division** function in C for **fixed**-**point** numbers?
I am using ac_**fixed** header but apparently that doesn't work since I'm getting zeros when I do 1/a where "a" is a **fixed**-type with values between 30-60.
Thank you,
Elnaz

Digital Signal Processing :: 11-20-2011 03:33 :: Elnaz :: Replies: **3** :: Views: **1000**

Hello,
I need to
1. convert integer to **fixed** **point**
2. Then perform functions such as **division** and exponential equation
Do you know any library or function for this? I know about mega functions but that is for floating **point** and it will require alot of resources that will be needed for other computations in my (...)

PLD, SPLD, GAL, CPLD, FPGA Design :: 07-20-2011 15:09 :: chikaofili :: Replies: **0** :: Views: **1653**

i wanted to implement **fixed** **point** format **division** in verilog. can anyone help me?

PLD, SPLD, GAL, CPLD, FPGA Design :: 06-12-2011 17:26 :: student13 :: Replies: **0** :: Views: **2034**

hi all
i need yours help for some little implementation algorithm in FPGA
i am using uart that gives me 7 bytes of ascii codes , 6 bytes on integers and one byte of **point** in that way XXX.XXX
i need to create a floating **point** vector - i mean to sub x"30" from each integer byte and collect the integers to floating **point** vector/ (...)

PLD, SPLD, GAL, CPLD, FPGA Design :: 05-20-2011 16:06 :: itmr :: Replies: **1** :: Views: **654**

what problem are you getting? general refusal or timing failure?
I would never use the "/" operator directly because it offers no pipelining. For a decent clock speed, you will need several pipelining stages, which is probably why you are getting failures. Altera and Xilinx ofer **fixed** **point** divider IP blocks.

PLD, SPLD, GAL, CPLD, FPGA Design :: 05-17-2011 20:50 :: TrickyDicky :: Replies: **1** :: Views: **661**

Arithmetic functions (e.g. sqrt, **division**) are operating on numbers, not bits. These numbers have a digital representation. The first **point**, when thinking about lookup tables, is to specify numeric ranges and resolutions, then about a suitable numeric format, mostly **fixed** **point**.
There's a large amount of contributions (...)

Microcontrollers :: 02-02-2011 08:57 :: FvM :: Replies: **3** :: Views: **2244**

Hi,
maybe this links helps
)
High speed **fixed** **point** **division** in FPGAs
ECE 645 Spring 2009
regards

PLD, SPLD, GAL, CPLD, FPGA Design :: 02-02-2011 06:32 :: qieda :: Replies: **7** :: Views: **3232**

You have to do it by hand, using shifting operations for multiplication and **division**.
I had a similar situation for color conversion functions. I replaced floating **point** operations to **fixed** **point** operations. Target multiplication and **division** operations first.
--
Amr

Microcontrollers :: 06-23-2010 15:44 :: amraldo :: Replies: **5** :: Views: **1200**

So the value will always be between 0 and 1 and I require upto 3 decimal places.
Binary arithmetic doesn't know decimal places. You have to choose a suitable representation for the result first. My suggestion
would be a binary **fixed** **point** format with a factor of 2**10. It can be easily achieved by extending the numerator to 34 bit

ASIC Design Methodologies and Tools (Digital) :: 03-27-2010 16:25 :: FvM :: Replies: **2** :: Views: **2055**

Today's HDL synthesis tools don't support Verilog or VHDL floating **point** type, but you can use **fixed**-**point** techniques instead. For example, 0.02 is approximately equal to 1311/65536, so you could multiply by 1311, add 32768 (for rounding), and then right-shift by 16. For higher accuracy, use larger terms in the ratio.

PLD, SPLD, GAL, CPLD, FPGA Design :: 04-01-2008 20:02 :: echo47 :: Replies: **14** :: Views: **6526**

Hello dear,
I need algoritm/ guideline on fiexed **point** **division** in vhdl.
Secodnly, how to check that in how many cycles FPGA performs an operation(i.e. +, -, / etc.).

PLD, SPLD, GAL, CPLD, FPGA Design :: 06-20-2007 10:21 :: info_req :: Replies: **4** :: Views: **2724**

hi everyone
can anybody help me in writing a code in fpga for divsion
**division** which is for signed number s n also for **fixed** floating **point**
plz
thanks

PLD, SPLD, GAL, CPLD, FPGA Design :: 10-17-2006 04:49 :: Anoz :: Replies: **2** :: Views: **1485**

Hola namqn,
I recall a FPU, probably that one, which had a **fixed** delay for reading its data of about 200 usec? Is it this one?
Good to keep in mind, before buying.

Microcontrollers :: 07-23-2006 22:56 :: atferrari :: Replies: **7** :: Views: **3945**

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