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## Fixed Point Fpga |

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floating point fixed point , fixed point , fixed point multiplier , fixed point vhdl

floating point fixed point , fixed point , fixed point multiplier , fixed point vhdl

46 Threads found on edaboard.com: **Fixed Point Fpga**

I am looking at the Altera DE0, DE1 and DE2 as well as the Xilinx/Digilent university ranges of boards to try out some DSP programming. I also want to be able to process FFT's.
The issue appears to be which **fpga** will do full floating **point**, or **fixed** floating **point**. I am not
clear on the issues but my initial thoughts are (...)

PLD, SPLD, GAL, CPLD, FPGA Design :: 02-27-2017 19:39 :: robinaspey :: Replies: **1** :: Views: **416**

it is entirely based on your inputs.
What is the range of input numbers you want to divide and or find square root.?
based on that only , **fixed** or floating is selected.

Digital Signal Processing :: 09-28-2016 11:42 :: srizbf :: Replies: **2** :: Views: **869**

Digital Signal Processing :: 08-20-2016 12:30 :: FvM :: Replies: **11** :: Views: **1322**

Hi All,
I need to implement a tapped FIR filter in a Xilinx **fpga** using VHDL . This means that i will need to do **fixed** **point** multiplication and addition.
I have read through some of the post on the xilinx and edaforum and not closer to understanding the best way to represent **fixed** **point** numbers in VHDL (...)

PLD, SPLD, GAL, CPLD, FPGA Design :: 08-15-2016 14:22 :: GhostInABox :: Replies: **9** :: Views: **2830**

Hi All,
I have to implement a tapped FIR filter which has **fixed** **point** coefficients. I am considering using the proposed IEEE **fixed** **point** package.
From what I have read on Xilnx and edaboard forums the package does not seem to give correct synthesizable results and/or is not well supported.
I am not sure if these issues (...)

PLD, SPLD, GAL, CPLD, FPGA Design :: 08-15-2016 14:40 :: GhostInABox :: Replies: **0** :: Views: **3**

Present implementations of ieee.float_pkg are only formally synthesizable but don't produce useful code due to lack of pipelining. You better refer to float IP provided by **fpga** vendors like Altera, Xilinx etc. Floating **point** arithmetic consumes considerable **fpga** resources, in most cases you better use **fixed** (...)

PLD, SPLD, GAL, CPLD, FPGA Design :: 06-15-2016 11:13 :: FvM :: Replies: **21** :: Views: **4792**

95 to 99 percent of mixed signal designs (digital processing of analog signals) are coded using **fixed** **point** numbers. Common digital audio or video systems are using it, too. As said, real isn't synthesizable, floating **point** is useful only for a very limited application range. Why do you think to need real numbers?

PLD, SPLD, GAL, CPLD, FPGA Design :: 05-20-2016 16:12 :: FvM :: Replies: **2** :: Views: **547**

Seems so. I guess you are trying to apply the exp() function to **fixed** **point** numbers which is apparently not supported.
I fear you need to get rid of the idea that arbitrary arithmetic can be put into **fpga** without thinking a bit about number formats and how particular functions can be synthesized in hardware. I would expect that the hdl (...)

PLD, SPLD, GAL, CPLD, FPGA Design :: 11-23-2015 09:34 :: FvM :: Replies: **1** :: Views: **652**

Hi,
I am reading a 14-bit signed value from a 14-bit vhdl port into a 16 bit signed variable in Nios II. There is no way for me to define it as 14 bits since the standard are alt_8, alt_16 and alt_32.
I define it as[/FONT

PLD, SPLD, GAL, CPLD, FPGA Design :: 05-28-2015 07:51 :: wannaknow :: Replies: **10** :: Views: **2343**

Often, we may want to carry out arithmatic in our **fpga** design which means that this shall be implemented in the RTL. Under such circumstances, is it a good idea to merely write C=A+B, C=A-B in the RTL or does one create an adder of the correct size in RTL, instantiate it and then use that instance to carry out the aritmatic? My question also applie

PLD, SPLD, GAL, CPLD, FPGA Design :: 04-16-2015 11:17 :: matrixofdynamism :: Replies: **11** :: Views: **1079**

sir
i want to design one model where input and output both are **fixed** **point** . if we will give some selected input then output should be its corresponding output. i have written a code is it write?
library IEEE_proposed;
use IEEE_proposed.**fixed**_pkg.ALL;
entity inv_q is
port ( address : in u**fixed**(1 downto -2); (...)

PLD, SPLD, GAL, CPLD, FPGA Design :: 02-23-2015 11:34 :: lokesh@88 :: Replies: **1** :: Views: **595**

Instead of the abstract real type, synthesizable logic uses float or **fixed** **point** numbers. Read about it!

PLD, SPLD, GAL, CPLD, FPGA Design :: 02-17-2015 23:12 :: FvM :: Replies: **1** :: Views: **736**

real type is not synthesizable.
Generally use real library for generating constants in code only. You have to convert floating **point** numbers to **fixed** **point**.

PLD, SPLD, GAL, CPLD, FPGA Design :: 08-31-2014 15:50 :: axcdd :: Replies: **2** :: Views: **1221**

Hi again,
Yes, I went through that. The component simulates now. I rechecked my requirements: for the dividends and divisors I use , the result will be always a positive number such that 0

PLD, SPLD, GAL, CPLD, FPGA Design :: 08-07-2014 09:11 :: zermelo :: Replies: **6** :: Views: **1175**

Hi,
I am trying to do a code for do division using verilog that is work with **fpga**. The thing is division operator is not syntyhesizable.I am using **fixed** **point** arithmetic to represent a number (includes fraction),think the only methode to do it is loop baised substraction methode or quotient remainder methodeIis there any other (...)

PLD, SPLD, GAL, CPLD, FPGA Design :: 07-30-2014 11:44 :: dipin :: Replies: **20** :: Views: **8444**

i want to calculate rms values of some signals.
xrms = sqrt{ 1/n*( x_1^2 + x_2^2 + ...... + x_n^2 ) }.
but the problem is sqrt operation. i have used cordac but it does not gives precise values u can either give integers or fractions. I have also tried sqrt function from **fixed**_alg_ug pkg but its not synthesizable because it depends on real_ma

PLD, SPLD, GAL, CPLD, FPGA Design :: 02-25-2014 07:12 :: habbas33 :: Replies: **5** :: Views: **925**

hello everyone
I built a simple model in dsp builder that returns the product of two constant number for example 2 by 1. I used dsp builder advanced blockset. when I set the data type in **fixed** **point** and verify the vhdl code in **fpga** it works and I can see the result in signal tapII. but when I set the data type as SINGLE (floating (...)

PLD, SPLD, GAL, CPLD, FPGA Design :: 11-22-2013 16:15 :: katayoon_1 :: Replies: **0** :: Views: **733**

The best advice I can give you that goes for a lot of "floating **point** on **fpga**" projects:
step 1: reformulate your problem so it can be done with **fixed** **point** arithmetic
step 2: use lookup tables a lot
step 3: interpolate a lot
step 4: enjoy the peace of mind after escaping the floating **point** headache. (...)

PLD, SPLD, GAL, CPLD, FPGA Design :: 11-08-2012 16:58 :: mrflibble :: Replies: **9** :: Views: **2632**

Hi ALL
in now days i design **fixed** **point** FIR that wil be implemented on **fpga**
the filtering unit using cic decimation followed by 2 fir LPF.
the input to the unit is 32 bits - 30 fractions and 2 for real number.
the end of the unit in 57 bits and i take just the fractions -51 downto 22.
when i analyze the FILTER FREQUENCY RESPONSE (...)

Digital Signal Processing :: 05-06-2012 07:26 :: itmr :: Replies: **0** :: Views: **820**

I'm looking for any book/document/app notes on binary arithmetic, numerical representations, and **fixed**-**point** math. I eventually want to implement arithmetic on an **fpga**. Most of the things I've been finding are too sparse and sometimes not coherent, I'm looking for a something that actually ties things together as I'm not very familiar with (...)

PLD, SPLD, GAL, CPLD, FPGA Design :: 04-03-2012 16:31 :: BlackHelicopter :: Replies: **3** :: Views: **849**

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jtag atmel | pin address | rc5 code pic | post simulation layout | spi lpc | ntsc and pal | pll issue | spice netlist | pwm microcontroller | library and models proteus