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Fixed Point Fpga

46 Threads found on edaboard.com: Fixed Point Fpga

Recommendations for university style development board for DSP

I am looking at the Altera DE0, DE1 and DE2 as well as the Xilinx/Digilent university ranges of boards to try out some DSP programming. I also want to be able to process FFT's. The issue appears to be which fpga will do full floating point, or fixed floating point. I am not clear on the issues but my initial thoughts are (...)

floating point representation in FPGA

I'm developing a low cost ultrasonic anemometer using fpga. The calculations include division and square root of fractional numbers which has to be coded using verilog. Can u suggest whether fixed or floating point representation will be convenient if low cost and accuracy are my primary concerns?

Fixed point Math for FFT, DSP in FPGA

fixed point numbers are commonly called integers (whole numbers). They are called fixed point because the decimal point is implicit always at the rightmost position. Not particularly. Integer (0 fractional bits) is only a special case of fixed point (scaling factor = 1). (...)

fixed point multiply accumulate in VHDL for Xilnx FPGA

from the following code , what does the synthesizer which supports the fixed_point package do ? , does it insert additional logic to manage the binary point ? , but the adder synthesized would be the same as the integer one right ? If both fixed point numbers have same number of fractional bits, the package (...)

fixed point addition and multiplication in VHDL for Xilinx FPGA

Hi All, I have to implement a tapped FIR filter which has fixed point coefficients. I am considering using the proposed IEEE fixed point package. From what I have read on Xilnx and edaboard forums the package does not seem to give correct synthesizable results and/or is not well supported. I am not sure if these issues (...)

How to implement floating point numbers in vhdl

Present implementations of ieee.float_pkg are only formally synthesizable but don't produce useful code due to lack of pipelining. You better refer to float IP provided by fpga vendors like Altera, Xilinx etc. Floating point arithmetic consumes considerable fpga resources, in most cases you better use fixed (...)

95 to 99 percent of mixed signal designs (digital processing of analog signals) are coded using fixed point numbers. Common digital audio or video systems are using it, too. As said, real isn't synthesizable, floating point is useful only for a very limited application range. Why do you think to need real numbers?

i have used hdl coder in matlab 2015 but the following errors appears in image

Seems so. I guess you are trying to apply the exp() function to fixed point numbers which is apparently not supported. I fear you need to get rid of the idea that arbitrary arithmetic can be put into fpga without thinking a bit about number formats and how particular functions can be synthesized in hardware. I would expect that the hdl (...)

How to read signed values from FPGA in VHDL to Nios II system

Hi, I am reading a 14-bit signed value from a 14-bit vhdl port into a 16 bit signed variable in Nios II. There is no way for me to define it as 14 bits since the standard are alt_8, alt_16 and alt_32. I define it as[/FONT

Arithmetic in FPGA design

Often, we may want to carry out arithmatic in our fpga design which means that this shall be implemented in the RTL. Under such circumstances, is it a good idea to merely write C=A+B, C=A-B in the RTL or does one create an adder of the correct size in RTL, instantiate it and then use that instance to carry out the aritmatic? My question also applie

fixed point representation

The code is basically correct and synthesizable, as far as I'm aware of. I would use to_ufixed() for a visual representation of literals. If the look-up table is intended for synthesis in internal block RAM, it may need registered addresses, depending on the used fpga family.

fpga floating point problem!!!

Instead of the abstract real type, synthesizable logic uses float or fixed point numbers. Read about it!

FPGA synthesizable verilog code with floating point numbers

real type is not synthesizable. Generally use real library for generating constants in code only. You have to convert floating point numbers to fixed point.

FPGA Linear interpolator, problem in difference terms

Hi again, Yes, I went through that. The component simulates now. I rechecked my requirements: for the dividends and divisors I use , the result will be always a positive number such that 0

division in FPGA using verilog

Hi, I am trying to do a code for do division using verilog that is work with fpga. The thing is division operator is not syntyhesizable.I am using fixed point arithmetic to represent a number (includes fraction),think the only methode to do it is loop baised substraction methode or quotient remainder methodeIis there any other (...)

sqt function required for rms calculation

i want to calculate rms values of some signals. xrms = sqrt{ 1/n*( x_1^2 + x_2^2 + ...... + x_n^2 ) }. but the problem is sqrt operation. i have used cordac but it does not gives precise values u can either give integers or fractions. I have also tried sqrt function from fixed_alg_ug pkg but its not synthesizable because it depends on real_ma

problem with verifying dsp builder advanced blockset single data type on FPGA

hello everyone I built a simple model in dsp builder that returns the product of two constant number for example 2 by 1. I used dsp builder advanced blockset. when I set the data type in fixed point and verify the vhdl code in fpga it works and I can see the result in signal tapII. but when I set the data type as SINGLE (floating (...)

FPGA-based floating-point logarithm unit

The best advice I can give you that goes for a lot of "floating point on fpga" projects: step 1: reformulate your problem so it can be done with fixed point arithmetic step 2: use lookup tables a lot step 3: interpolate a lot step 4: enjoy the peace of mind after escaping the floating point headache. (...)

Question about cutting bits in fixed point FIR

Hi ALL in now days i design fixed point FIR that wil be implemented on fpga the filtering unit using cic decimation followed by 2 fir LPF. the input to the unit is 32 bits - 30 fractions and 2 for real number. the end of the unit in 57 bits and i take just the fractions -51 downto 22. when i analyze the FILTER FREQUENCY RESPONSE (...)

Need a Book or any Documentation on Binary Arithmetic and Fixed-Point Math

I'm looking for any book/document/app notes on binary arithmetic, numerical representations, and fixed-point math. I eventually want to implement arithmetic on an fpga. Most of the things I've been finding are too sparse and sometimes not coherent, I'm looking for a something that actually ties things together as I'm not very familiar with (...)