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217 Threads found on edaboard.com: Formal
133010 I could not view the internal signal even though I am using the formal format *ghw with , , , and Anyone ?
Good Day, i am a novice programmer and am trying to compiler a code for micro controller AT89C52 using a reference code but i keep running to an error which seems to be causing other errors. this is the code void timer1_ISR (void) interrupt1 //timer1 interrupt service routine { TR1=0; //stop the timer1 time_c
Hello, As suggested in previous posts, you should refer to some verilog textbook. you need to understand how a verilog module is instantiated and its ports are connected to other modules/signals. Any basic verilog tutorial should give you clarity to understand what is formal and actual port name in module instance. i.e. in your case LUT6 is a mo
Hello, I would like to know the best book for formal Verification for a complete newbie? Any useful links are also appreciated. Best,
Lambda/10 works, sure. There is no formal IEEE definition as far as I'm aware. The "size" is usually considered to be the radius of the smallest possible sphere that encloses the entire antenna.
hello all, pls help me to find out is reason for this. should i have to run "verify" command after that because ii'm not getting any answer. Info: Net i:/WORK/usb_link_ulpi/link_dbg is undriven. Info: Net i:/WORK/usb_link_ulpi/link_dbg is undriven. Info: Net i:/WORK/usb_link_ulpi/link_dbg is undriven. Info: Net i:/WORK/us
I am getting the following two errors: Error (10346): VHDL error at comparator_TestBench.vhd(17): formal port or parameter "beginGame" must have actual or default value Error (10784): HDL error at comparator.vhd(8): see declaration for object "beginGame" and both are related to assigning a default value for beginGame in my comparato
The majority of microcontroller families of current designs offer one or more UART, SPI, I2C and other interfaces, and could most likely handle your current design tasks. While there are many considerations when choosing a particular microcontroller, three of the primary concerns are: 1. The formal specifications and required tasks of the design.
formal verification is a very complex subject that a few people fully understand, and I have to admit I am not one of them. Fishing for compliments? Anyway, thanks for the profound explanation.
Hi all! I'm running formal equivalence on RTL to Gate-level netlist. One of the errors that i encountered is the reset DFF's of revised is connected directly to ground and in the golden the reset is connected to the GSR. However, when i used the option set flatten model -seq constant, the in-equivalence was gone. How was this happen? I really
Hai all, I am planning to start a vlsi startup in bangalore and presently making a broad plan of action for the startup. Major areas of focuses are in in-house developed formal Verification method and IP core any comments and suggestion are welcome....:arrow:
Hello, In the design which I am working on, I need to pass a std_logic_vector(15 downto 0) from a register in the top module to an input port of a sub module. I have done it in the following way: -----top_module---- signal ConfigMem_Wire : std_logic_vector(15 downto 0); {Register_module} register => ConfigMem_Wire
formal tools called property checkers can mathematically prove that, given an RTL design and some assumptions about the relationships of the input signals, an assertion will always hold true. If a counter example is found, the formal tool will provide details on the sequence of events that leads to the assertion violation. If this is true, do we
Hi, I am wanting to do a design in VHDL I am been mandated to use semi formal design methods such as Yourdon which does not map well to describing hardware. Which modern methods would people suggest and how to bridge the gap between Yourdon and modern methods?
I have no formal formation in electronic, but I do have some knowledge. I know what a flip flop is, but I don't want have to use clock to add. Why 8 bits? I don't know, I just thought that would be a good challenge and it's better to have more bits to do an ALU with more functions. But that's more a long shot. Anyway, I am not concern if the logi
Hi all! Im new on using the cadence tool COnformal Ultra LVR. It says that "Conformal LVR enables formal verification of the final SPICE netlist against the golden RTL or final gate-level netlist to ensure that the design taped out is functionally equivalent with golden RTL and the final gate-level netlist." My question is that what is (...)
Hi all, I am comparing RTL vs netlist using conformal and when I do vpx analyze noneq , I get 30+ of these errors(similar ones as below): I have used all modelling directives. Tried set flatten model -seq_constant, remodel -seq_constant -repeat but it seems to be increasing my non-eq points instead of resolving them. Please let me kno
Hi, I get the following Modelsim error when compiling my design for simulation: "# ** Error: tx_and_replica.vhd(362): Actual (function call "to_sfixed") for formal "i_x" is not a globally static expression." The relevant code snippets are: 1) Port mapping: Line 362 is the s_tx_tmr conversion to signed fixed. U_ITPL_TTL_HIGH: li
I think the formal definition of the Mealey machine will directly lead to a mapping from present states x input alphabetes to next states and output alphabet, which can be coded in a ROM.
Conformal-LEC is a program that checks logic equivalency in formal verification which means the mathematical verification of the logic of a circuit. however i found test vectors when debug. why there is vector?