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267 Threads found on edaboard.com: Fpga And High
Hi all, Have a nice day !! I may implement my digital design using fpga. Once the design is synthesized, i may read the HDL netlist file to introduce some design modifications, but i want to insert the logic at high fan-in and also high-fanout internal nets. In this regard, i want to know "is there any (...)
Hi all, Have a nice day !! I may implement my digital design using fpga. Once the design is synthesized, i may read the HDL netlist file to introduce some design modifications, but i want to insert the logic at high fan-in and also high-fanout internal nets. In this regard, i want to know "is there any (...)
Hi, please give more informations: * are you designing a I2C master, slave or both? * How are you designing? HDL? PLD, fpga, ASIC, discrete logic? *** I need to guess: (HDL and fpga, I2C master) Then you should have a high frequency master clock, where you generate SCL. Then synchronize your SCL line (read back from IO) (...)
This project based on kintex 7 fpga. In simple case, I need to transmit high volume of "RAW" data to fpga. Using file system isn't required. A colleague of mine had tested the free SATA II core from Opencores and was able to transfer (only RAW) data from an Artix7 fpga to an external HDD. I don't know about (...)
I need high speed communication from the PC to a custom fpga board. I already tried USB2 chips in USB-TO-FIFO mode. But I want a faster chip. So I thought of using USB3 protocol. Which chip can I use? I don't want to use FTDI chips now and I think Cypress is a good choice. Cypress provides FX3 chips which are compatible with USB3. Is FX3 (...)
I'd an A/D device (one with a good evaluation board) first... and from there, choose an fpga evaluation board that can communicate with the A/D evaluation board. The FMC interface is pretty common.
A solution is to use a counter that generates the required clock and connect its output to a buffer that then feeds into the DAC. Is this approach a good idea? What are the drawbacks? If a fpga PLL can't be used then try out the counter approach with a sufficiently high master clock. But use only 1 master clock and use (...)
As mentioned in your previous thread , you need to look for the hardware features of your fpga family. E.g. Cyclone V doesn't provides registers between multiplier and adder. I'm not sure for the high performance fpga families.
There has been work on this for many years. I know AMD shipped opteron chips with fpgas connected over 10 years ago, but I think the main problem with these was the throughput between dual processor and fpga wasnt really fast enough. There is this article from 2006 about server acceleration using fpgas:
Is it 40 Mbit/s or 40 MByte/s ? With 40 Mbit/s you can use LVDS and the old UART protocol. You may have to design the UART yourself, but it is easy. With 40 Mbyte/s = 320 Mbit/s you will have some trouble unless your fpgas have high-speed serial transceivers or Gigabit ethernet.
Hi, i am making an IGBT gate driver. Ground of the driver will have high voltage like 3000V and Vc of the driver will be 3015V. there will be also fpga which will read datas such as Ig, Uce, Uge... from ADC. I am a bit confused how should be fpga part of the circuit, should it also has 3000V ground? it doesnt (...)
Hello, I have to design a packet processor on the fpga ZC7020. I have a buffer, fragmentation unit, framing, parsing etc blocks. My payload size is 9 MB. The data to the buffer comes from a IDT SDRAM which has 16 bits I/O. The buffer has to be as big as to accumulate 500 bytes of packet which is my MTU size. Next it has to send this 500 bytes pa
Hello, I have a very high speed design implemented into Virtex-5 fpga operating at 500MHz. I am using ISE14.7. The design is fully placed and routed with no errors and warnings ! Also, the post place&route simulation results are great. Now, I am looking a way how to assure that this design works properly in reality while (...)
Hi, In my project , I need to adapt an fpga card to read data from 4 CAN network at least. Beacuse i didn't found an fpga including more than 2 CAN controllers. i īm wondering if there is a solution for this. I read that is possible to emumate CAN bus with RX TX I/O of the fpga with an IP core but i dont't find more information of how it (...)
hi I want to learn and design professional high Speed PCB Boards for fpga etc. I have a work experience on Orcad 16 Layout 16 and have designed RF Power Amplifier PCB's up-to 2GHz using ADS. What are the leaning steps involved and which tool is required (Altium, PCB Editor etc)? Do i need to follow any (...)
I need high performace dvb-t demodulator ip core based on xilinx fpga!
Hi Guys, This is not a technical question. I am interested in improving my knowledge on high Speed Digital Communication Systems (LVDS, high speed interfaces design in fpga), could you guys suggest or recommend me some links where I can read and also try to design them on fpgas. I am focussing in Machine (...)
Hiii, I want to design a PCI Express Card v3.0, i googled and found that every body is using fpga for designing PCIe cards, Can i use micro controller/Processor for designing PCI Express card instead of fpga, if possible please suggest me relevant controller or processor, Anybody please help me with this issue Thanks&Regards Viswanath
Hi, it is possible to generate a pseudo random generator. You may use itīs output to generate a new signal. Inside the fpga you shouldnīt call this a "clock", because a clock is considered to be stable with a defined frequency and constant duty cycle. You may call it a "clock enable" signal. Outside the fpga you (...)
Hello everyone, I want to make PWM LEDS, i mean that pwm signal will control the intensity/brightness of the leds, such as this video: But how it could be possible when we have only '1' state which is 100% of brightness and '0' state which is 0% of brightness..? With pwm I can only change the frequ